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TMS3779-Q1/TPS3780-Q1 Datasheet Question

The datasheet SBVS273-JUNE2016 lists two voltage ranges and the device operation in each range:

8.4 Device Funcitonal Modes

8.4.1 Normal Operation (VDD >= VDD(min))

          Output signals react to SENSEx pins

8.4.2 Power-On-Reset (VDD < V(POR))

          VDD less than VPOR,  outputs undefined.

But there's nothing said about the third range, when    VDD(min) > VDD > V(POR).

Is the operation in this range undefined?  If so why is there even a V(POR) spec?

  • Hi Anthony,

    Perhaps the easiest explanation of the states of any SVS is the Timing Diagram (copied here for your convenience).

    Very Respectfully,


  • Thanks Ryan,

    So there is a functional mode for VDD(min) > VDD > V(POR)?

    And it's basically to operate but with a 570us delay?

    Is there a reason that the Undefined time and the Startup Delay (TSD) both happen to be 570us?

    It would seem it's just saying that this is the worst case reaction time to transitions through the VIT-/VIT+ region whether they
    occcur on initial power up, or going into or out of a brown out.

    But I notice that the 'Undefined' areas in the drawing are not marked with the <- tSD -> Parameter which is curious if they then happen to be the same value of 570us.
  • Hi Anthony,

    The output is normally held low when Vdd is in this middle region. There is a point (undefined in the datasheet) above which the output begins to respond to the sense inputs (similar to a UVLO). However, while Vdd is below below Vddmin, the comparator is not fully operating at the specified accuracy so the output may not be in the expected state (high when Sense is above the threshold, low when sense is below the threshold).

    Very Respectfully,
  • Hi Ryan,

    Hmm. The problem I have with that statement is that most embedded processors for which this type of device is designed to support,
    do actually require a VPOR that is lower than the VDD(min) spec [much lower, in fact it's desireable usually to start pulling reset by 0.5-0.6V].
    What is flexible is the amount of current that can be pulled at this low voltage level; but in most cases by the time the voltage being monitored reaches VDD(min) this is very much too late as the logic on the embedded processor would have started operating already but is out of spec.

    The way the datasheet is written is probably fine, but two things are odd are:

    1) 8.4 Device Funcitonal Modes doesn't actually talk about the operation between VPOR and VDD(min) which is of critical interest to the application.

    2) the 570us delay in response is a tad bit on the 'long' or 'slow' side but I think that it's workable ...

    But if we cannot rely on the supervisor at least starting to drive the reset output low at the VPOR point during power on, then this is going to make it not useable. I think that's not what the datasheet actually says but it's what I read in your last post. The datasheet is almost ok but leaves some gaps that would be good to fill in.