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UCC28631 Latching off on (re)power

Other Parts Discussed in Thread: UCC28631, UCC28633, UCC28630, UCC28632

(specifications at bottom of post)

A problem concerning a flyback switcher using the UCC28631.  If left alone for long enough, it will start up with no problem.  If repowered, sometimes it will come up, sometimes it will not.

Monitoring Vdd on the switch side, it seems that if I repower the supply while the chip is in t_reset, it will cause the chip to low-power latch mode ("locked up" below).  What is going on?  What is causing the latch?  How do I avoid it, or detect and clear it?

I have checked that I am meeting the constraints outlined in the datasheet:

Rcs/Lpri < Eqn 15 and Eqn 16

120u < Kline_adj < 350u, Eqn 17

Vcs_slopecomp < 30mV/us,, Eqn 51 [I think there is a typo in eqn 51, which I corrected.  is that incorrect?]

10k < Rthevenin < 20k


50W output offline/DC flyback switcher

Vin: 85-264Vac and 100-300Vdc; Vout: 12V@ 4.2A

Measurement taken at 125Vdc in, 0.5A CC active load output

Rp deviated from recommended 3.9k to 4.42k per this discussion thread and linear approximation of bench measurements


Lpri=275uH; ratio 13:2:2        Rcs=0.2R        (values tweaked from calculated to meet stability criterion)

C_Vdd=20uF     (problem still occurs at 10uF)

Ra=30.1k                 Rb=44.2k

  • Patrick,

    Since there are only a small number of latching faults on the UCC28631, it can only be one of the pin-fault protections that is being triggered. Is it possible for you to post your full schematic? If not, then you could also email it to me separately. Is the HV pin of UCC28631 connected to the AC input, or to the bulk cap positive terminal?

    To help debug which one is occuring, I would recommend that you probe the SD pin (pin 2) of the UCC28631 after the latched fault has tripped (the region where VDD is regulated between ~ 8-10 V). Every time VDD hits the upper level ~ 10 V, the fault cause is detectable by a pulse train on the SD pin.

    The fault-code pulse train starts with a ~30-us positive pulse (start-pulse - can used for scope trigger), then a train of ~1-us positive pulses, then a low interval of ~10 us to signify end of the pulse train. Count the number of 1-us pulses in between the start/end.

    The possible faults in this case are as follows:
    21 - VSENSE pin fault - short, or open detected, or Rth out of range
    22 - DRV pin fault - short detected
    23 - CS pin fault - short or open detected

    In this case, I think I already know what's going wrong, and I believe that you will get code #23 - CS fault. The reason is that since Rp is a higher value, the line UV protection will allow the power stage to operate down to a much lower bulk cap level than normal before giving up for line UV.

    Therafter, the IC will charge VDD through the HV pin to ~15 V start level, will generate 3 "exploratory" switching cycles in order to measure Vout and Vbulk via the aux winding, and then detect that Vbulk is too low to start. After ~1 sec wait in low power mode, VDD gets discharged to ~5 V and the whole sequence repeats. And this is what's seen on your scope plots to the left of the green arrow labelled "will not lock up".

    After this, things change becasue the Vbulk level has continued to fall, and has now fallen below a critically low level. During the 3 exploratory pulses, the CS pin level is also checked during the switch on-time. A level of ~50 mV is expected at the pin due to current flow in the external shunt - anything less is considered a potential short to GND on the CS pin. Depending on the value of the magnetising inductance and the external Rcs shunt, at a low enough bulk cap voltage level, the di/dt of the primary current will become so shallow that a level of >50 mV on the CS pin is not reached during the primary on-time. Then the CS pin latched fault is triggered. This has already been triggered at point "a" in the scope plot above. In latched fault mode, the IC goes into low-power sleep mode, and then regulates VDD between ~8-10 V by turing the HV current source on as required. At point "a" above, the IC is in sleep mode, so VDD falls slowly.

    At the point where the orange and red arrows meet, VDD has fallen to ~8 V, so the HV pin is used to try to charge VDD. However, since the bulk cap level is so low, even though the HV startup current source is on, the internal sleep-mode IC consumption exceeds the available HV current, so rather than have VDD ramp up as expected, it continues to fall, albeit at a shallower rate. When VDD has fallen below ~7 V even though HV is trying to charge it up, this is detected as a possible AC removal/disconnect (since HV is normally connected to the AC side of the bridge through dedicated diodes), the latched fault is reset, VDD drops to 5 V, and the cycle repeats from point "b".

    The next time VDD reaches 15 V, the CS fault will trip again, hence the VDD waveform follows a similar shape. However, in this case, before the latched fault can reset, AC is re-applied, which charges up the bulk cap, increases the available HV charging current, and the latched fault mode persists as normal.

    With the HV pin connected to +Vbulk (as I suspect it is in this case), if the lathced fault trips, it will take a long time to reset after AC removal, since the bulk cap has to be depleted down to the levle where VDD cannot be recharged (< ~30 V from above plots). If the HV pin was connected to the AC side, the latched fault would release and reset almost immediately after AC removal.

    In this case, if the HV must be connected to the DC side +Vbulk, then a series zener diode can be placed in the feed to the HV pin (similar to D10 in the EVM schematic - by choosing the zener voltage, the min bulk cap level below which the HV pin can't charge VDD can be controlled - and the min bulk levle can be set to higher level where the CS fault can't be tripped. E.g. by using say 62-V zener, the HV pin can't try to restart with Vbluk < ~60 V, avoiding the CS fault. But as long as the re-applied AC input > 42 V ac, it will increase bulk cap level and allow HV pin charging - albeit very slowly initially until the AC input is high enough that there is more charging voltage available on the HV pin. At 80 Vac, there will still be ~51 V on HV. If the startup time is too slow in this case, the HV series resistance can be decreased, or the zener voltage dropped slightly.

    I think this fully explains what you are seeing, and hopefully adding a zener on HV pin can resolve the issue for you.

    If so, please click the "verify answer" button.

  • Thank you for your fast response and detailed answer!

    Checking the code at the SD pin, it is indeed fault #23.  The HV pin is connected to V_Bulk through two series 100k resistors, and the explanation given is consistent with other circuit behaviors observed (e.g. if V_Bulk drops low enough, Vdd does not reach V_start the "lockup" behavior does not occur).  Adding a 68V zener in series with the two 100k resistors (anode to HV pin) did solve the problem - I was unable to cause the supply to "lock up" across the VIN range, and Vdd quickly dropped to below V_reset.

    A further question: we do connect the HV pin to the bulk line, as indicated in Figure 15 b) in the datasheet for the DC case.  Is there any issue with connecting the HV line directly to the AC/DC in side in for the UCC28631, using the same topology as the datasheet Figure 15 a)?  This may also be a solution that removes the potential issue of increased startup time (though may introduce brownout lockup issues).

    System in running fault..  CH1: V_Bulk   CH2: Vdd   CH3: SD


    SOLUTION - System with 68V zener blocking HV.   CH1: V_Bulk   CH2: Vdd

  • Patrick

    I am glad to hear that the zener diode resolved the issue.

    Regarding the HV pin connection:
    - For UCC28630 & UCC28633 it MUST connect to the AC side, due to the X-cap discharge feature, DC on the HV pin will look like an AC disconnect.

    - For UCC28631 & UCC28632, the HV pin can be connected to AC or DC, both will work.

    If HV is connected to the DC side, it will start slightly more quickly (higher average voltage available to charge VDD cap). After power off, the repeated restart attempts will also help to deplete the bulk cap over time, after AC removal. However, it does run the risk of attempted restart at very low bulk levels, and risk tripping the CS pin fault as seen. But there is a proven solution to this by adding a blocking zener to set the min bulk cap level where startup/restsart can begin. There is also the downside that if any latchign fault does get triggered, it will take longer for the fault to reset, since the bulk cap must deplete to ~30-V level.

    If HV is connected to AC, startup time is slightly longer. But any latched faults reset in < 1 s after AC removal. Since the HV pin is powered from the AC side, it will not attempt to restart after AC removal, so there is less risk of trying to restart with low bulk cap level, and trip the CS fault protection. However, from first startup with discharged bulk cap, if the AC input is increased very very slowly, it is still possible for the first startup attmept to be made with bulk cap level ~30-40 V as it charges up very slowly, and possibly trip the CS protection fault. A lot harder to make it trip, but certainly possible under the wrong set of conditions. Putting a blocking zener on the HV pin will also prevent this fault from being falsely triggered, same as with DC on the HV pin.

    The AC-side connection of the HV pin needs 2 dedicated rectifier diodes for full-wave feed. It can also be half-wave fed through a single diode, at the expense of approx. doubled startup time.

    I can see pros and cons of DCand AC connection of the HV pin, it depedns on what matters most for your application.