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UCC28880 stability issues (Ref data sheet Eq 19)

Dr. Ramkumar Ramaswamy
Intellectual 400 points
Other Parts Discussed in Thread: UCC28880, UCC28881

Hi:

I have built a 5V high side buck converter around the UCC28880 almost identical to the circuit in EVM-616. This shows a stable output under low load but a sawtooth oscillation under 50mA load. Looking at the datasheet, equation 19, I see that there could be a potential problem with the time constants. That equation says that the time constant Cfb X (Rfb1 + Rfb2) should be about a tenth of the time constant CL X RL, because the voltage across Cfb is not updated in real time. I also see that the evaluation board EVM-616 schematic has been designed that way. However the catch is that the RL X CL time constant obviously changes as soon as you connect a load and therefore this 1/10 relationship falls apart. . In my case the numbers are as follows:

Rfb1 =  39k, Rfb2 = 9.1k (output = 5.4V), Cfb1 = 2.2uF.  CL = 47uF, RL = 10k

This gives me a value of 105ms for Cfb X (Rfb1 + Rfb2). The moment I connect a load that draws 50mA, RL has effectively dropped to 100 ohms. Now the
RL X CL time constant is 4.7ms and that means that the time constant of 105ms is way too high: it should be a tenth of RLXCl = 0.47ms! The datasheet says that if Cfb X (Rfb1 + Rfb2) is too high then the output voltage may drop. Perhaps this is what is happening - drastic drop in output voltage followed by an attempt by the feedback loop to pull it back up etc.

Can A TI engineer help with this formula which apparently seems to break down in this case? What am I missing?

Thanks - Ram

  • 0
    Intellectual 400 points

    Further to the above - I tried changing the output capacitor to 330uF, so as to increase the output RL X CL time constant to 66ms (with a load current of about 22mA). Then reduced the feedback capacitor Cfb to 0.1uF so as to change Cfb X (Rfb1 + Rfb2) to 4.8ms. There is significant improvement in the situation but I still see ~0.1Vpk oscillations on the output. Any insights by other users of this chip would be welcome. Thank you!

  • 0 in reply to Dr. Ramkumar Ramaswamy
    TI__Mastermind 31580 points
    Hi Ram,

    I have asked one of the LPCC applications engineers to respond to this post.

    Regards

    Peter
  • 0 in reply to Dr. Ramkumar Ramaswamy
    TI__Guru 74325 points
    Hello Ram,

    The Cfb and Rfb just set the timing of the PWM packets delivered to the output. It is not a real time sample of the output as you mentioned. The capacitor selection for the feedback is just a starting point and you have to adjust it for best performance. I do agree with you the equation in the data sheet only represents one load point and does not cover all load points.

    I found the same thing as you did. When you decrease CFB the output ripple voltage decreases. This however penalizes load regulation. This then requires more pre-loading even adding a clamp to the output.

    The UCC28881 is a similar device and the EVM uses a much smaller capacitor for Cfb with a zener clamp to keep the output in regulation as the load decreases. www.ti.com/.../sluubb6.

    I do recommend if you are going to use the UCC28880 in a high side buck with this sampling scheme that use a small Cfb capacitor and a Zener clamp to regulate the output under light load conditions; as the UCC28881 EVM uses.

    Regards,

    Mike
  • 0 in reply to Mike O'
    Intellectual 400 points

    Thank you Peter for your follow-up, and Mike for your insightful answer. My product is in a prototyping stage so I will plan to change the chip to UCC28881 in the next iteration. As an immediate measure I will use a zener clamp across the output capacitor CL which I see is also spoken about in the datasheet.

    1. Could using the clamp possibly interfere with the feedback loop and cause loss of feedback at low loads when the voltage tries to rise - thereby causing some potential instability at low loads?

    2. What are the factors guiding the lower bound on Cfb (or on the associated time constant)  with UCC28880, currently set to 0.1uF? I suppose it would have some relationship with the switching frequency. Complementary question: anything limiting the upper bound on the load capacitor CL, currently set to 330uF?

    3. The UCC28881 specs do look better - anything I "lose" in moving to this chip apart from a slightly higher cost?

    Thanks - Ram

  • 0 in reply to Dr. Ramkumar Ramaswamy
    TI__Guru 74325 points

    Hello Ram,

    1.  In the high side buck design Cfb and Rfb set the timing of the PWM packets.  It is really not a feedback scheme unfortunately.

         > Cfb is only charged during the freewheeling period when the free wheeling diode is conducting and the output voltage is higher than the voltage presently on Cfb.

         > When the FB pin is below 1V the controller allows switching at roughly 62 kHz.

         > When the FB is above 1V switching is terminated.

         > I found the best performance of this device is to set the Cfb capacitor as low as possible and used a clamp to regulate the output at lighter loads.

         > A series pass regulator on the output might even be a better choice versus a clamp.

    2.  In a high side buck this converter operates as if it is open loop with this sampling scheme.  You can set the Rfb and Cfb per the data sheet but it will only be accurate for one load point as you have discovered.  I believe that is better just to set the Cfb capacitor as low as possible and let this device run open loop.

    3.  I used the UCC28881 as example to show that Zener clamps have been used to help regulate the output on these devices.  You don't necessarily have to switch to the UCC28881 if the UCC28880 meets your requirements.

    This device is an economy buck controller with and internal FET that deliverers 62 kHz PWM packets with internal peak current limiting.  This device also runs open loop in this configuration and external circuitry is required to regulate the output. 

    Regards,

    Mike

     

  • 0 in reply to Mike O'
    Intellectual 400 points

    Thank you Mike, greatly appreciate the detailed answers and I believe I understand the product better now. In particular the sentence in the datasheet that now makes more sense and which I now wish I had read more carefully is "[in] traditional high-side buck the voltage feedback is sampling the output voltage VOUT, making the DC regulation less accurate and load dependent than in low-side buck configuration." Darn!

    Will implement your suggestions. Again, thanks for the great support!

  • 0 in reply to Dr. Ramkumar Ramaswamy
    TI__Guru 74325 points

    Hello Ram,

    I was glad I could help and good luck with your design.

    Regards,

    Mike