• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 62 subscribers
  • Views 380 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TWL6032 peripheral support, documentation, drivers for watchdog

Aaron Jones
Intellectual 760 points
Other Parts Discussed in Thread: TWL6032

Hi Team,

We are using some SOM with OMAP onboard, and SOM has external TWL 6032 (Power Management Chip).

While there is just a little information of hw characteristics publicly available, we cannot find programming guide how to get use of it, neither we can find driver code available to integrate it in our project.

We figured out, so far, that among multiple features provided, like RTC or Battery charger, there is no code to demonstrate how to use watchdog. And the documentation we have is not comprehensive enough to deduce programing sequence for Watchdog, hence we are seeking for advice.

From the Data Sheets we have, it is clear that watchdog is supported (SWCS057C_TWL6032_Data_Manual_11_07_2011.pdf, section 4.4.5 Primary Watchdog Reset, page 47).

The register description  of PRIMARY_WATCHDOG_CFG (SWCU095_TWL6032_ES1 1_Register_Map_12_02_2011.pdf, section 2.3.14 PRIMARY_WATCHDOG_CFG register, page 62) and  PHOENIX_LAST_TURNOFF_STS Register (SWCU095_TWL6032_ES1 1_Register_Map_12_02_2011.pdf, section 2.3.4 PHOENIX_LAST_TURNOFF_STS register, page 50) give some idea on the operations, but the limitations and overall sequence is not obvious.

 

Main questions:

  1. In the notes of PRIMARY_WATCHDOG_CFG description, there is a statement that “The primary watchdog can be disabled by an EPROM bit”. How can we read the EPROM bit to make sure watchdog is enabled on the SOM we have?
  2. If WD supported on 6032 we have, what would be the correct sequence to initialize, activate, de-active and configure primary WD, as it could be more than just writing values to register; and could WD be activated/de-activated in run-time?
  3. Section 4.4.5  Primary Watchdog Reset instructs that if DEVOFF_WDT bit is not cleared within timeout after the WD reset sequence, and WD get expired  again then  6032 generates reset forcing device to WAIT-ON/OFF state. Does it mean that device (4470) will be hold in reset state, and the question is how to get out of this state, or avoid to be in this situation as our device is unmanned, and we could not reset it by external means on will.

Regards,

Aaron

  • 0
    TI__Intellectual 1360 points
    Aaron,

    1. We disable the primary watchdog for development samples. For production units primary watchdog will be always
    enabled by OTP with no capability to disable it by software.

    2. At inital power up, processor reset signal NPESPWRON=0. After the power ON sequence, NPESPWRON pin is released, and the WD counter starts with default value. The processor must reset the WD counter, by writing to PRIMARY_WATCHDOG_CFG before the timer expires. The WD value is determined by the processor. If the processor does not reset the WatchDOG_CFG register, the Switch off transition is initiated by the PMIC

    3. After watchdog timer expires, the part stays in Wait-ON/Off state and DEVOFF_WDT bit is set to 1. To get out of reset state, processor has to clear the DEVOFF_WDT bit and do a software reset by SW_RESET bit in register PHOENIX_DEV_ON.

    Let me know if you have any further questions.

    Thanks,
    Jay