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TLC5917: Startup Timing for TLC5916 / TLC5917

GLENN R PETERSON
Prodigy 30 points
Part Number: TLC5917

I'm switching the TLC5917s' Vdd to minimize the quiescent current of the TLC5917s when no loads are active.

Question: How long after applying Vdd does the MCU have to wait before starting to clock data in.

Details: -OE is held at Vss.  Six devices are cascaded.  Clock frequency is 250 KHz.  Vdd is 3.3v, Vled is 5v, Current is 12 ma. but the LEDs have resistors to Vled to minimize power dissipation in the TLC5917.  Special Mode is NOT used.

The MCU currently applies Vdd and then waits 5 ms. before starting to send the serial data.  There are no issues, but I'd like to reduce that time, hopefully to a few microseconds.  I just didn't find documentation on the initialization.

One option is no delay, but send seven (7) bytes of data for the six (6) TLC5917s.  The first byte would be all zeros and hopefully would be ignored.  But if startup is fast enough, I can avoid the wasted time.

Thanks, G. Peterson

  • 0
    TI__Expert 3460 points
    Hi Glenn,

    Since the setup and hold times for the TLC5917 are listed in ns (in the datasheet), you should wait around 5us before sending the SDI information.
  • 0 in reply to Harry Kennedy1
    Prodigy 30 points

    Harry:

    Thanks, but I don't understand where the 5 uSeconds comes from in the Datasheet.  I have Rev D.

    I see no documentation referring to the time from when Vdd is applied to when I can start sending data to the device.

    It might be there, but I just looked again for it and did not find it this time either.

    Perhaps you could identify the "setup and hold time" parameter(s?) by name or table and line number.

    Thanks again,

    GP

    As I said in the initial forum post, I'm switching Vdd because the quiescent current is (about) 10 ma, power the off-grid system cannot afford when nothing is being powered.

    For comparison, the MCU is using less than 100 uAmps, so the four (4) TLC5917s would use about 400x the power of the MCU if I didn't remove Vdd when nothing is powered.

  • 0 in reply to GLENN R PETERSON
    TI__Expert 3460 points
    Glenn,

    This parameter is not explicitly stated in the datasheet, but is based off the other design parameters.
  • 0
    TI__Expert 4035 points

    Hello Peter,

    In theory, it would be no delay or a very short delay time after Vdd voltage built-up then inputting clock data because the logic circuit could work under 3.3V, So you can try to reduce the wait time furtherly to double confirm it. but waiting a short time is safer.

    BRs,

    Ryan  

  • 0 in reply to Ryan Hu (BSR-MV)
    Prodigy 30 points

    Ryan:

    Thanks.

    I've measured the fastest my code can go from powering the TLC5917 to sending the first CLK and it's about 7 instructions.  [I could make it faster by unrolling a loop and putting a routine inline, but I don't need the speed.]

    At 1/4 MHz instruction rate (slow to save power), that's 28 microseconds.  So I think there won't be an issue given the 5 microsecond recommendation.  I've removed all artificial delays and with two sets of four TLC5917s I haven't seen any issues.

    But I don't like depending on non-documented behavior.  That's why I started the thread - to see if I could get official information.  I guess I have semi-official information and will have to proceed on that basis.  :-(

    I also measured the rise time at the Vdd pin.  It's less than 35 nano-seconds.  The LP0701 is a great P-FET for switching power on and off for external chips (such as the TLC5917).

    Thanks again,
    Glenn

  • 0 in reply to GLENN R PETERSON
    TI__Expert 4035 points
    Glenn,

    Glad to hear that! You could move on now.

    Ryan