TPS650842EVM-116: TPS650842 modifying/questions on boot sequence

Hi Kevin G,

1) At what point does LDOA1 come up? It’s not shown in the boot sequence

[KL] - LDOA1 can be enabled by I2C, not controlled by any of the control pins so it is not part of the sequence for this OTP. It can be part of a sequence or always on but it is not for the TPS650842 OTP.

2) What is the output frequency for LDOA1? Their DDR ideally wants 0Hz to 250 KHz.

[KL] What do you mean here? Bandwidth?

3) How do we go about modifying the output on some of the buck regulators? Such as changing LDOA1 from 3.3V to 2.5V? Looks like it’s from modifying the registers in the firmware? Not hardware changes?

[KL] Correct, all voltages are controlled by internal register (volatile) settings which can be modified by I2C. Note that they are reset in the event of a power fault, falling edge of PMICEN, etc.

4) How would we hook up the control inputs SLP_S4B,SLP_S0iXB, SLP_S3B signals? Doesn’t the TPS650842 require feedback from the SoC to go through its boot sequence?

[KL] Correct, those control pins connect to the BSW SoC. PMICEN is typically controlled by a microcontroller but can be done discretely if desired. DDRVTTCTRL and DDR_SEL are typically just tied high / low.

5) Is it possible to change the boot sequence for the TPS650842 if we needed to?

[KL] No. The sequence is stored in the one time programmable memory (OTP) which is loaded upon first power up. Custom OTPs would have different part numbers (TPS65084X).

Let me know if you have any other technical questions.