CSD18542KTT: CSD18542KTT with gate ringing issue

Kai, 

I don't think TI ever wrote its own app note on paralleling FETs because there is already extensive literature on the process from our competitors - I know IR has a good one in addition to AOS. 

However we have written two app notes about ringing reduction. The first may not apply as much because I believe it is with regards to surface mount devices but the second may be applicable to you. 

In addition, if you want to provide a schematic, I can ask one of our apps engineers to take a look and see if they have any advice. I could not find a datasheet for the comp part you mentioned above, so that would be helpful/necessary if you wanted our team to take a deeper look. 

Dear Brett 

Below attached file is the test report ,so far ,when we add external ferrite bead can solve this issue 

But due to we don't reserve the series resistor on the gate side ,Have any chance to solve this ringing issue with modify the layout 

Thanks 

4064.BQ76930 application issue.docx

Kai,
I'll let you know what our apps team says

I showed your schematic to our apps team. This is what they had to say:

"They either need to keep the Ferrite bead or change the layout… This Gate oscillation is a common problem when you parallel FETs and needs to be controlled via resistors, beads, or an ideal layout."