In a condition where the power supply is not enabled - either due to the EN pin being low, or the AVIN being under its UVLO threshold - is the lower FET conducting and connecting the SW output to GND internally, or is the SW output simply left floating? The data sheet does not describe what's going on in the control logic.
-
Ask a related question
What is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
