• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 62 subscribers
  • Views 1272 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS54318: About relationship between the SS cap and Vout start up delay time

Tsukui Yusuke
Guru 21930 points
Part Number: TPS54318
Other Parts Discussed in Thread: TPS54218,

Hi,

Could you tell me about relationship between the SS cap and Vout start up delay time?
Please confirm the attached file.
TPS54318 waveform.pdf

When changing the capacitance of the SS capacitor,
A difference occurs in the delay time until the output voltage starts.

I got two questions from customers.
Customer wants this information in order to form a FPGA power sequence.

1. Reason why the delay time is different.
2.Relational expression between the SS capacitor and the delay time.


Best Regards,
Yusuke/Japan Disty

  • 0
    TI__Guru**** 191445 points
    So far as I can tell this has not been specifically characterized. It is dependent on several variables, some of which are application specific. At EN rising edge, there is some deglitch and delay before the IC sees itself as enabled. Then the band gap and other internal circuits must be initialized. At this point the SS capacitor will start to charge. Is the SS voltage increases above 0V, the error amplifier will begin to charge the COMP pin RC network. When the COMP pin voltage rises above the minimum clamp voltage, the device will begin to switch. Probably the largest variable here is the COMP pin charging time, which is very much application dependent.

    See this thread for the very similar TPS54218 which is a 2 A version of TPS54318:
    e2e.ti.com/.../569234
  • 0 in reply to JohnTucker
    Guru 21930 points

    John-san,

    Thank you tell us about the deglitch time.
    However, when checked on the evaluation board,
    there is a relationship between the SS capacitor and deglitch time.

    SS cap=2.2nF  : deglitch time is 40us
    SS cap=0.01uF : deglitch time is 80us
    (Only changed part is the SS capacitor.)

    Increasing the SS capacity tends to increase the deglitch time.
    Could you tell me about this cause?

    Best Regards,
    Yusuke/Japan Disty

  • 0 in reply to Tsukui Yusuke
    TI__Guru**** 191445 points

    I do not doubt there is some difference with SS cap size.  When I researched this previously, this was not characterized.  I can ask about it again, but I think it was not accounted for.

  • 0 in reply to JohnTucker
    Guru 21930 points

    John-san,

    Thank you for dealing with this matter.
    SS capacitor dependent delay time can be reproduced using EVM.
    Could you please review this issue again?

    Best Regards,
    Yusuke/Japan Disty

  • 0 in reply to Tsukui Yusuke
    Guru 21930 points

    Hi,

    Can I get the information?
    Customers need that information for design.
    If you need more information or if  I should  clarify my comment ,
    please let me know.

    Best Regards,
    Yusuke/Japan Disty

  • 0 in reply to Tsukui Yusuke
    TI__Guru**** 191445 points

    There is approximately 40 mV of offset between VFB and SS.  So SS must charge up to 40 mV before the error amplifier starts to charge the COMP pin above the minimum clamp and start the converter switching.  t = Css * .04 V / 1.8 uA.  These are typical numbers.  There may be some variation.