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UCC27533: UCC27533 Glitch On Start-Up

Part Number: UCC27533

I have a customer seeing the following issue with the UCC27533:

My circuit is pretty simple. VDD and IN+ are tied together. IN- and GND are tied together. A decoupling capacitor of 100n is put right across VDD and GND. My application has this circuit excited with triangular pulses. During the voltage ramp up at the VDD, I see a small pulse at the output. It is happening before the voltage builds up to working voltage of UCC27533. I am simulated the same circuit in TINA using the model of the IC, I do not see this happening. I appreciate if you can help me on this. Is the startup operation glitch free? I saw another similar driver, which specifically mentions glitch free start up.



The current I have shown in earlier scope shot is the current that charges the decoupling capacitor. This current may have not gone through the pull-down resistor of IN+. I have lifted the IN+ and left it open; as per datasheet with any input open, the output should be low. I do see the glitch part still coming.

As per the functional block diagram, irrespective of the logic levels at input, as long as VDD is less than working voltage (8-9V), the output should be low. The glitch occurs at much below voltage.

It seems to me that there should not be a “glitch” in the start-up of this part. Can you look at this issue and let me know what you think is happening?

Thanks for your help with this!

Richard Elmquist

  • Hello Richard,
    I am Richard Herring who is an Apps Engineer with the High Power Driver product line.
    I am curious what function the customer is looking for with the circuit. It looks like a pulse generator turning on at UVLO rising and off at UVLO falling. There might be a cleaner way to do the function.

    Regarding the behavior. Low side drivers are typically anticipated to operate with a modest VDD rising rate. There will be a UVLO delay during turn on, which you see in the waveform.

    Regarding the output response, or initial glitch. With a more modest VDD rise time, when VDD is initially rising the driver output is clamped to the VDD capacitor by the body diode of the internal driver (high side) MOSFET. When VDD reaches ~1.5 to 2V there is enough voltage to actively drive the internal low side, sinking device to ground.
    The 35V drivers will require a higher VDD level to drive the low side to ground, than a 15 or 20V driver.

    With this circuit you are showing, it would be worth looking at devices at have additional output clamping circuits, which I assume the one you mention as "glitch free" would have in place.
  • Richard,

    I am sorry for the delay in responding, but I have a couple further questions.

    Is the UCC27533 "g;itch free"? The reason I ask this is because in Table 1 under VDD UVLO Protection it states that the device should have "glitch free" operation. Can you explain this in more detail as your comments seem to indicate that this is not the case.

    Are you saying that the Vdd rise rate is part of the issue? Is it too fast? Please explain your statement in more detail so that I can explain this to the customer.

    Thanks for your help with this!

    Richard Elmquist

  • Hello Richard,

    I do see the comment as you mentioned. I will confirm the IC structure with IC design, but most low side drivers are as I had described earlier, which I can look to illustrate, or explain in more detail. as you requested.

  • Richard,

    Are there any updates on this issue?

    Please let me know if you have any further questions for the customer.

    Thanks for your help with this.

    Richard Elmquist

  • Richard,

    I did discuss with IC design, and they commented that the fast VDD rising time of 500ns or less is resulting in the output perturbation.

    The output clamping is as I mentioned before: At very low VDD (<~1.5 to 2V), the output is clamped to the VDD capacitor through the driver MOSFET body diode (~0.6 to 0.7V Vf). When VDD is 1.5 to 2V there is enough voltage to actively drive the internal MOSFET pulldown device.

    I have a couple of questions: Is there any capacitive load on the driver output? This is expected in normal applications.

    Can the customer use a lower VDD rated driver? Some of the lower voltage drivers have a lower VDD level where the internal devices can actively clamp to ground.

  • Hello Richard,
    I wanted to follow up since this conversation is still open.
    The last response I sent from design inputs was that the fast VDD rising time of 500ns or less that is in this application is resulting in the output perturbation in this circuit.
    Is the customer still pursuing this design approach? There may be a better way to implement their circuit depending on what the desired requirement is.