TPS62177: Transient on Output During Startup

Thanks for posting your schematic and waveforms.

So, does any point on the IC connect to anything else on the PCB, except for the input voltage (adapter)? i.e. the output, PG, and SLEEP pins don't connect to any other circuitry?

Does this same behavior occur on all PCBs that you made? How many have you tested?

Can you post your PCB layout around the IC?

Hi Chris,

thanks for the timely response! Apologies that mine took some time, full day, and took some time to properly assemble a meaningful picture of what's going on there with components, and some things that I've tried...

First in answer to your questions:

1. Sleep is connected to a microcontroller pin, and was originally pulled down. Meaning the regulator would start (after bootstrap) into sleep-mode. This was our objective, then allowing the uC to pull it out of sleep during boot. In the board as modified (and pictured...) I moved R67 from the original layout position as a pull down to correspond to a debug hack of pulling it up. We saw the behavior regardless of being pulled up or down (via same 100K). This pin is still connected to the uC, who's pins default to Hi-Z on startup (set to inputs)

The waveforms in the last post correspond to Sleep pulled up via 100K to the output node.

2. PG was connected to the uC as well (uC is powered by this regulator). We had intended to use PG to modulate RESET on the uC, but found that we may have had too high a current draw in its "idle loop" ( no real FW yet, just canned stuff) due to the regulator defaulting to SLEEP mode. We removed the components which connect PG to RESET. They are independent now, and PG is pulled up as shown in the schematic.

So, the schematic as shown should be a honest representation of the circuit, less that sleep is still connected to a uC pin which defaults to "input", though it's reasonable there is a "race" going on depending on how the regulator and uC interact on startup. Do note, however, the transient we're observing is generally >100ms.

3. We have tested two boards so far. Trying to be conservative until we understand a bit more about what's going on.. They are not very reworkable in many regards (lots of tiny parts and BGAs) so we're taking it slow so we don't trash them before we get far in out bringup. :-)

4. Please find enclosed a PDF. Took a bit of magic to assemble a meaningful picture. 

The PDF contains a number of labeled layers. It's not perfect, but if you play with turning on and off the layers, you can see the component placement and the copper pattern. Some things to note:

- The original layout puts the input and output caps on the opposite side from the inductor and IC (I didn't do the layout, I just get the pleasure of making it work! ;-)). The cap is coupled to the output inductor with a single via. Not the best, and I'm sure you would immediately point this out as bad practice regardless of the problem we're seeing. 

- The inductor and IC are on Bottom.

- The pullup resistors are on the Top as are the caps. 

Use the Layers in an Adobe Acrobat viewer to turn on and off the components and copper to see how things are built.

- I moved C64, the output cap, to the same side as the IC and Coil (C64 Hack layer). With this, the output cap is very closely coupled with the inductor, and to a GND close to the package as shown. 

The C64 hack had zero impact on the presence or behavior of the transient as shown in the scope traces. 

One of the things that was noticed, and why we posted two pictures. It looks kind of like the high-side fet is stuck on, as you can see the output following the input in one of the pictures. The adapter is rated at 1.25A, and is a switching regulator, so it may have some responsive current limit, as the +12 is also dragged down a bit. Remember, the output of the regulator is now completely unloaded. 

After posting this, I will do two more experiments:

a. Stronger pullup on Sleep
b. Cut the trace for Sleep leading to the uC. 

I don't expect either of these to make a difference, but if they do I'll report back.

Any insights into this or some clues as to potential startup conditions for us to be aware of and respect would be gratefully appreciated!

Best Regards,

kenRegulator Composite Layout.pdf

Thanks for posting your layout. I did not see any GND vias tying all the GNDs together. Are there some? Can you point out where they are located?

As well, how many total layers is the PCB?