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TPS783: Enable thresholds and hysteresis

Part Number: TPS783

I have a low power application where I want to control the startup and shutdown of a sensor subsystem that operates from a 3V supply. Energy is harvested and charges an EDL capacitor. The voltage from the harvester ramps linearly and I want to accumulate enough energy to run the system for a known period before allowing power to flow through to the load. That requires a start threshold (ON) voltage of around 2.75V and stop (OFF) threshold under 1.8V. The TPS783 is a nano IQ regulator with an enable pin with well-defined thresholds of 1.2V (on) and 0.4V (off). Normally this would be connected to a logic signal however with such a large hysteresis band and high input impedance, I connected it to a voltage divider on the VIN side of the regulator to use it as a level detector in the following configuration:

See plot 1.

I then did a transient run with a ramping source to investigate the turn on and off points. It seems to work quite well and is already close to my required turn on threshold which can be further optimised by adjusting the voltage divider. The turn off point is effected by the supply which is ramping down and dropping out at about 1.4V. The following plot shows the response:

See plot 2.

If this works in real life it has the potential to save me having to use a separate nano power reference and comparator to drive the enable pin with a saturating on/off transition. It does however rely on the enable thresholds being reasonably consistent between devices. There is also a potential for higher than expected quiescent current as the enable pin sees an analogue ramp rather that fast transition. I analysed this issue using the Pspice model provided and could not see any evidence of this.

My question is to the design group to advise if this approach is reasonable and also to request more information on how well characterised the enable pin thresholds are and how they are implemented. If they are tied to the internal reference in some way then I would expect them to be quite stable. Please advise further on this?

Thanks and Regards,

Dean Cooper.

Plot1:

Plot 2:

  • Hi Dean,

    The EN pin can be used like this, but, there is variation in the threshold across temperature and devices.  See figure 9 below for typical behavior.  For this reason, I would not anticipate any higher accuracy than what the data sheet limits have listed for VEN(HI) and VEN(LO).

    Regards,

    Mike

  • Hi Mike,

    Thanks for responding. This is a classic case of "read the manual". I'm always in such a hurry these days I sometimes omit that step. Yes Fig 9 clearly shows the enable pin thresholds and is exactly what I was looking for. VEN(LO) has a TC of about -1mV/degC and VEN(HI) has a TC of about -0.3mV/degC. This is quite workable in my case. I would say these must be tied to the internal reference and If so, would expect their initial tolerance to be similar at about 2%. The Pspice model is however miles out if the Fig 9 thresholds are correct. It places VEN(HI) = 1.3V and VEN(LO) = 0.7V at 27degC. Not to worry however and I'm going to consider this question as answered. The next step will be to test a real part.

    Thanks and Regards,
    Dean.
  • Hi Dean,
    Good to hear the part will work. In general, the PSPICE models are designed with only 25C modeling, we don't typically design models at extended temps.

    Let me know if anything else comes up.

    Regards,
    Mike
  • Hi Mike,

    I didn't do a temperature sweep, just left the model at its default. I would say the simulated thresholds are not even close to Fig 9. Still it may be that they are not accurately modeled. The model is encrypted which makes it difficult to investigate further from my end. You may want to mention this to the model team for them to have a look at when time permits. I ordered some samples and will let you know how they go on the bench.

    Thanks and Regards,

    Dean.