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UC3825A: Current Limit, Soft Start, and Clock Modifications

Ryan.Bishop
Expert 3900 points
Part Number: UC3825A

Hello,

I received the following questions from one of my customers. Please let me know if you need more information. Thank you!

Ilim pin -- Can this be configured for the hiccup over-current/short circuit during startup and normal operation?  I tried on simulation, but do not see it.  It is left open now.  How to implement? Currently there is a CS transformer for cycle by cycle current limiting only.

Soft start -- Can a soft start cap be discharged to turn off the converter? Is the bigger cap an option for soft staring the output and controlling over shoot? Also controlling the inrush upon PWM startup?

Clock -- Can an external clk be used directly at pin 4 instead of resistor and cap at pins 5 & 4?  In simulation I have OR-ed two 200kHz out of phase clocks to clock the part with 400kHz so each output switches at 200kHz. The simulation does not have a problem but just wanted to make sure of this.

-Ryan Bishop 

  • 0
    TI__Intellectual 1550 points
    Hi Ryan,

    Please find my response to your questions below:

    ILIM pin: no, UC3825A doesn't have hiccup function.

    Soft start: Yes I think so because as you can see in the block diagram on page 1 of the datasheet and also the statement on page 8, when SS is low, the error amplifier output is forced low which cause the PWM comparator output to go low. By raising the SS cap, the inrush current will be reduced while the startup time is increased.

    Clock: Ideally yes, but practically not appropriate. Because if you look at Fig. 4, the CLK_LEB signal is not a pure square wave. The slope of the falling ramp of that signal controls the pulse width of the LEB signal which is needed to blank out the noise seen at the current sense signal that you will definitely see in the practical application.

    Let me know if you have further questions.

    Regards,
    Wangxin
  • 0 in reply to Wangxin Huang
    Prodigy 70 points

    Hi,

    So, what about creating a shallow fall of the clock with a RC and use that at pin 4?

    thx    

  • 0 in reply to Bob Aivati28
    TI__Intellectual 1550 points
    The shallower the fall of the clock, the smaller the leading edge blanking period. If LEB period becomes too small, it might not be able to blank the noise/spike of the current sense signal.
  • 0 in reply to Wangxin Huang
    Prodigy 70 points

    I thought the faster clk fall will produce the smaller blank time?I have a fat clk.  Wanted to artificially slow the fall time to have some blanking period if needed Are you saying is the other way around?

    thx  

  • 0 in reply to Bob Aivati28
    TI__Intellectual 1550 points
    Sorry for my typo. I meant the faster the fall, the smaller the LEB period. You are correct.