We are using the PMIC TPS65921 for our design that makes use of an OMAP3 processor. Over the course of our signal integrity tests, we have found that multiple digital lines that are outputs of the IC are noisy, with the noise having the same frequency as the internal buck converters in the chip. We found that the noise was also in phase with the switching of VDD1. In our layout, we took care to use a separate ground plane for each buck converter (separate from our main ground except for one point below the GND balls of chip) and made sure to place sufficient decoupling capacitors on the digital supply and on the input and output of the VDD1 converter. We have also made sure that the balls belonging to the digital 1.8V input and the ground balls belonging to the buck converters are adjacent.
The digital line belonging to the ULPI clock and the main processor clock are both either generated or buffered by the TPS and enter the processor.
We would like to know if this is a known issue and whether there is a known method to minimize this noise.
Thank you very much,
Eli.
