HI Team,
For the TI LP8725TLE-D PMIC we are using on our product, the LDO and LILO output capacitance spec is:
We have found that with the maximum specified output capacitance of 20uF, the regulator turn-on voltage ramp rates are:
LDO 4 & 5: ~30mV/uS
LILO 1 & 2: ~25mV/us
One device on our board has a voltage ramp rate restriction of 18mV/uS, above which its ESD protection could be triggered.
To meet this ramp rate requirement we have had to increase total capacitance on these regulators to:
LDO 4 & 5 (1.8V): 48.4uF
LILO 1 & 2 (0.8V): 38.5uF
In both cases, only 2.2uF X7S 0402 ceramic is at the PMIC output
with the rest of the capacitance being at the load – to which these supplies are tracked (not planed).
I estimate the track resistance to the capacitance at the load to be at least 125mOhms – which the PMIC will see in addition to the cap ESR
Do you see any risks to the stability of these regulators?
What is the reason for the maximum capacitance specification on these regulators?
Reading online about LDO stability generally, it seems that too low ESR can be an issue – and higher value ceramic capacitors do generally have lower ESR,
but in our case this isn’t what the PMIC sees as these are at the load. Are there any other issues with high load capacitance?
The results of a quick load transient test in the lab with and without this extra capacitance don’t show any significant differences …
