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Compiler/UCD3138064EVM-166: Debugging program for UCD3138064EVM-166

Part Number: UCD3138064EVM-166
Other Parts Discussed in Thread: UCD3138

Tool/software: TI C/C++ Compiler

I want to change duty cycle in pin DPWM0A, please help me to do this. Also, unable to implement dead time between pin DPWM0A and DPWM1A. I am including my program below, please help me to implement 40% duty cycle in pin DPWM0A, which is showing 50% now. 

void init_dpwm0(void)
Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 0; //disable locally for init

Dpwm0Regs.DPWMCTRL0.bit.CLA_EN = 1; //default is 1 - use cla
Dpwm0Regs.DPWMCTRL0.bit.PWM_MODE = 0; //normal mode
Dpwm0Regs.DPWMPRD.all = PERIOD; //use .all for all values, make sure scaling matches.

Dpwm0Regs.DPWMEV1.all = PERIOD/2; //Put event 1 at start of period
Dpwm0Regs.DPWMEV2.all = (PERIOD * 3)/4; //1/4 of period - divide is OK because it's all constants.
Dpwm0Regs.DPWMEV3.all = 0;//1/2 of period
Dpwm0Regs.DPWMEV4.all = PERIOD/4; //3/4 of period
Dpwm0Regs.DPWMSAMPTRIG1.all = PERIOD; //3/4 of period

Dpwm0Regs.DPWMCTRL2.bit.SAMPLE_TRIG_1_EN = 1; //enable 1 sample trigger
Dpwm0Regs.DPWMCTRL1.bit.EVENT_UP_SEL = 1; //update at end of period

Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 1; //enable locally
//Dpwm0Regs.DPWMPHASETRIG.bit.PHASE_TRIGGER = 2; //8nsec phase delay


void init_dpwm1(void)
Dpwm1Regs.DPWMCTRL0.bit.PWM_EN = 0; //disable locally for init

Dpwm1Regs.DPWMCTRL0.bit.CLA_EN = 1; //default is 1 - use cla

Dpwm1Regs.DPWMCTRL0.bit.PWM_MODE = 0; //normal mode
Dpwm1Regs.DPWMPRD.all = PERIOD; //use .all for all values, make sure scaling matches.
Dpwm1Regs.DPWMEV1.all = 0; //Put event 1 at start of period
Dpwm1Regs.DPWMEV2.all = PERIOD/4; //1/4 of period - divide is OK because it's all constants.
Dpwm1Regs.DPWMEV3.all = (PERIOD)/2; //1/2 of period
Dpwm1Regs.DPWMEV4.all = (PERIOD * 3)/4; //3/4 of period
Dpwm1Regs.DPWMSAMPTRIG1.all = PERIOD; //3/4 of period

Dpwm1Regs.DPWMCTRL2.bit.SAMPLE_TRIG_1_EN = 1; //enable 1 sample trigger
Dpwm1Regs.DPWMCTRL1.bit.EVENT_UP_SEL = 1; //update at end of period

Dpwm1Regs.DPWMCTRL0.bit.PWM_EN = 1; //enable locally
//Dpwm1Regs.DPWMPHASETRIG.bit.PHASE_TRIGGER = 2; //8nsec phase delay


  • Setting dead times is pretty complicated, and depends on which mode the DPWM is in, which depends on what power supply topology you are trying to implement. 

    Generally you can directly set dead times only between the 2 pins on a single DPWM module. 

    To set dead times between DPWM modules generally involves a phase trigger where one DPWM is synced to another one.  Or you can use the intramux or edggen bits to have a DPWM module control other pins that its own.  Like I said, pretty complicated. 

    The various EVMs have good examples of how to use this complicated setup for different topologies.  If you are going to do a standard topology, it's a very good idea to start with these EVM codes.  The represent the intentions of the chip designers for that specific topology.

    If you want to do your own, I suggest studying the UCD3138 Technical Reference Manual, especially the DPWM section.  It has diagrams of the different DPWM modes showing how the pulse width and dead time are calculated. 

    For the case you have, with the DPWM in Normal Mode, and the CLA enabled, you need to change the filter output to change the pulse witdth.  The filter is also known as the CLA (Control Law Accelerator).  If the CLA is disabled, the pulse width is determined by the difference between Event 1 and Event 2.

    As I mentioned above, there is no direct way to enforce a dead time between pins of different DPWM modules. 

  • Is 40% duty cycle determined by the filter(CLA) or you want to operate in open loop mode?
    In case you are interested in open loop, then Dpwm0Regs.DPWMCTRL0.bit.CLA_EN should be set to zero.

    Also the following is problematic:
    Dpwm0Regs.DPWMEV2.all = (PERIOD * 3)/4; //1/4 of period - divide is OK because it's all constants.
    Dpwm0Regs.DPWMEV3.all = 0;//1/2 of period
    Because EV3 is sunstantially smaller than EV2, means negative dead time between A side and B side.

    Are you sure you are interested in normal mode? In normal mode when A outputs the duty cycle (D), B outputs (1- D).
    It is in Multi-Mode that A output and B can be set independently.

    Also Dpwm0Regs.DPWMSAMPTRIG1.all should not be set to PERIOD, this way it will never trigger.

    And RESON_DEADTIME_COMP_EN is usefull only in LLC resonant mode of operation and not in normal mode.

    Also to set certain deadtime beween DPWM0 and DPWM1, your better connect the two in a master and slave fashion.

    Please refer to the UCD3138 Technical Reference Manual for more details:

    If you need our help please send us an exact waveform drawing of DPWM0A/B and DPWM1A/B and I will send you the exact configuration program.

  • Thanks a lot for the suggestion. I can generate the desired signal by making Dpwm1Regs.DPWMCTRL0.bit.CLA_EN = 0.