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TPS7A8101: Start up delay

na na78
Guru 16770 points
Part Number: TPS7A8101

Hi

I have question about start up delay.

I'm referring Figure 29 from datasheet.

The circled point represents start up delay (~60msec).

Is there variation of this delay?

For example, is it normal if the delay would be 2msec?

I assume 3.3V to 1.2V regulation.

BestRegards

  • 0
    TI__Expert 4350 points
    Hi,

    Startup delay is measured from time when the UVLO threshold and Enable threshold are reached, until the time the output starts to rise.
    In the TPS7A8101 datasheet, Electrical Characteristics table, the UVLO minimum threshold is 1.86 V and Enable minimum threshold is 1.2 V.
    The part will be enabled with Ven >= 1.2 V, but the output will be held off until Vin >= 1.86 V for UVLO threshold.

    Startup delay will be in the range of 100's of usec to a few msec.

    LDO's have Undervoltage Lockout (UVLO) to ensure the LDO's internal circuits have the proper internal rails and biasing to allow for controlled output voltage. Vout will not start up until the device reaches UVLO minimum threshold.
  • 0 in reply to Eric.Preiss
    Guru 16770 points

    Hi Eric

    Thank you for reply.

    I attached waveform.  Could you show us your view?

    There is about 8msec delay from input over UVLO to output rising.

    VIN and EN are connected to Vcc together.

    Is it strange operation?

    Isn't is 

  • 0 in reply to na na78
    TI__Expert 4350 points
    Hi,

    Your scope shot shows expected behavior. Startup time up to 100 msec is normal for this LDO.

    The Electrical Characteristics table shows 80 msec as the typical startup time. Figures 25, 28, 29 show startup time. There is a mistake in the gridline numbers on the time axis for Figure 28. Ignore the 0.002, 0.004, etc. Time is 50 ms/div. I will get the datasheet fixed.

    This datasheet does not provide separate specs for delay and startup ramp time, only total (delay + startup ramp).