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LM5116: How to find converter MOSFETs power dissipation and their junction temperatures ?

Part Number: LM5116
Other Parts Discussed in Thread: PMP9333,

Hi, my LM5116 based converter works amazingly well but I want to find out the load limits by calculating the junction temperatures of the most vulnerable components - they are MOSFETs and inductance. The main IC is surprisingly cool not effected by the load increase. Inductance temperature says all about it, so I see the MOSFETs are the weakest point. My schematic mostly follows PMP9333 reference design :

My design is different only due to input voltage is higher (84V) and  to reduce turn-on ringing I use both HB resistor and HO high MOSFET gate resistor.

Junction temperature is calculated as Tj = Tc + (Kj x P)

where Tc is temperature measured at the top of MOSFET package, Kj is junction to top case coefficient , P - power dissipated inside the component . MOSFETs junction to top is known from datasheet - 18k/w ( I use Infineon BSC190N12NS3 )

How to find the individual component's dissipated power? Total power dissipated inside the converter 3.2W , efficiency 92% , how is this losses power distributed inside this design? Temperatures of both MOSFETs are equal which suggests that their power dissipation is about equal . If I know nothing better  I can just assume that all the dissipation happens inside the MOSFETs but it is surely not true.

Any suggestions?

  • If I knew the power loss in LM5116 and in the inductor for a given total power or for the known output current, deducting them from the total power loss in the converter would give the answer for two MOSFETs...
  • Hello Vlad,

    The losses in the IC will be minimal because you are feeding back Vout to the VCCX pin.
    The main losses will be in the FETs and you will see some losses in the inductor. You can estimate the power losses in the FETs by using the article in the link below.

    Hope this helps?

  • Thank you David. This link provided indeed answers the question well theoretically. Practically though I wouldn't go such a long way to estimate max power dissipation in MOSFETs - too much details specs gathering and computations for each MOSFET in a rather large whole project (ther are multiple parts in the project similar to this DC-DC converter). Interestingly this article reminded me another article (also provided by you in the past) calculating MOSFETs efficiency in the switchers :
    I like this last article , it shows some easy rough estimates based on conduction losses and I used it for rough estimate in this schematic.
    I assume that all losses spread between MOSFETs and inductor.
    INductor loss Pind = Iout x Rindinternal - ( how much this value depends on the switching frequency? meaning how precise is this power loss estimate in the Inductor?),
    both MOSFETs total loss = Ptotal - Pind
    each MOSFET shares losses equally since they are both the same and Rdson the same so
    Pfet = (Ptotal - Pind) / 2
    Although this approach wrongly applies power loss of LM5116 chip to the MOSFETs package but it makes whole estimate quick and more on the safe side :)

  • Hello Vlad,

    A couple of comments in response to your post.

    1. The losses in the inductor are made up of two parts.
    a. DCR losses which can be estimated to be Iout^2*DCR.
    b. Core losses. Sometimes this can be a little difficult to calculate because the data needed is not available. YOu can estimate that the Core losses ~ eaul to the DCR losses. Also the core losses are related to Switch frequency. The DCR losses are NOT.
    2. The losses in the top FET and bottom FET will unlikely be equal, because the top FET dissipates transition losses, where the bottom FET does not. Again, the article shared covers this. Wish you all the best in your design.


  • "You can estimate that the Core losses ~ equal to the DCR losses" - does it mean the Pind more likely to be = 2 x (Iout^2 x Rdcr) taking into account both parts of losses ?
  • That's Correct Vlad, just as an estimation, will be closer to this number...

    Hope this helps?

  • Thank you David - I just have to double inductance power loss in my rough estimate to apply your correction. The 2nd point there about differences between dissipation of top and bottom MOSFETs seems to be not important in practical terms because
    1. the same MOSFETs used - the same junction-to-top-case coefficient
    2. tests show the same measured case temperature at all ranges of the load (difference no more than 1-2C with pin thermocouple touching the top case)
    The same case temperature indicates that MOSFETs junction temperature and total power dissipation in both MOSFETs are the same. If the top MOSFET dissipates more of transition losses (Miller plateau ) as you mentioned then this means that the bottom MOSFET equally dissipates internal flyback diode losses or may be more of conduction losses ?.... but the total loss in both measured equal.
    Thank you again for your input.
  • Hello Vlad,

    Usually the FETs are closely positioned together so one FET typically leads in thermal temp rise but the temp will settle at temperature close to each other. Having said that, your assumption you mentioned above, could be true and is reasonable under certain operating conditions.

    Hope this helps?

  • indeed they are closely positioned and thermally influence each other- that is the reason why we measure touching the top spot of the case where the juncition-to-top coefficient is the highest (18C/W), providing additional thermal insulation from the shared board area . Blowing air fan thermally insulates even more the adjacent components by carrying away radiating heat before it influences the solid case of another package. This method seems to be workable because the output inductor is located as close to one of MOSFETs , yet shows significant temp difference. The more I think about it the more I am convinced that the bottom FET is dissipating more in it's flyback diode as an inductive "response" to the spikes in the top FET... whence making up for a total power loss