Hi
Please help check the attached file.3858.lmz23610 three models.docx
Please give some suggestion for this problem.
Thanks
Star
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Hi
Please help check the attached file.3858.lmz23610 three models.docx
Please give some suggestion for this problem.
Thanks
Star
Hi Star,
Thank you!
First of all, I suggest to check the syn clk signal. Cause the modules must be synchronized by a clock signal to avoid beat frequencies in the output voltage caused by small differences in the internal 359-kHz clock. If the modules are not synchronized, the magnitude of the ripple voltage will depend on the phase relationship of the internal clocks.
Secondly, from the schematic, I didn't see any bulky output capacitors. The datasheet states that a minimum value ranging from 330 μF for 6-VOUT to 660 μF for 1.2-VOUT applications is required based on the values of internal compensation in the error amplifier. And when you do paralleled output, the current sense gain of the entire system increases according to the number of modules slaved to the master. To compensate for this and ensure good stability, the total output capacitance has to be increased.
Regards!
Yangbo