• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 371 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS2H160-Q1: Transition delay

DY Ko
Expert 5110 points
Part Number: TPS2H160-Q1

Hello Team,

My customer asked about the transition delays of TPS2H160-Q1 as below.

Q1: How long does it take to detect when a fault occurs and then wait until the fault pin goes low?

Q2: How dong does it take for OUT1 and OUT2 to be off when the IN1 and IN2 go to Low?

       I think it depend on the output voltage level, output load condition, output capacitor and etc.

Best regards,
DY

  • 0
    TI__Mastermind 28200 points

    Hello,

    For Q1: please follow the timing limits in the datasheet. For example in over current, the deglich time is Tcl(deg) and limits are 80uS to 180uS. For open load in off state the deglich time is Td(ol,off) and limits are 400uS to 800uS.

    For Q2: please follow the timing in the datasheet. The time from INx goes low to Vout at 90%, is Td(off) and limits are 20uS to 90uS. The turn off slew rate dV/dT(off) is not related to Td(off). The datasheet limits 0.1V/uS to 0.55V/uS are for resistive load. For capacitive load the slew rate depends on the load time constant.

    Regards