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TPS65381A-Q1: CRC checking is handled differently after power up reset verses IGN pin reset.

Allen Hayward
Prodigy 150 points
Part Number: TPS65381A-Q1

I am using the process detailed in the note on page 61 of the product data sheet to do a test on the CRC checking hardware during DIAGNOSTIC mode.

From Datasheet:

While in the DIAGNOSTIC state, a check can be performed to confirm the CFG_CRC_ERR
bit is set to 1 on a mismatch between the value stored in the SAFETY_CFG_CRC register
and the value that is calculated from the configuration registers covered by the CRC8. If the
CFG_CRC_EN is cleared while the CFG_CRC_ERR bit is set to 1, then the device
transitions to the SAFE state, set the EE_CRC_ERR bit and clear the CFG_CRC_EN bit. To
avoid this transition to the SAFE state, the CFG_CRC_ERR bit must be cleared by running
the EEPROM CRC by setting the EE_CRC_CHK bit. While the EPPROM CRC is running,
the EE_CRC_ERR bit is set. Assuming the EEPROM CRC was good, both the
EE_CRC_ERR and CFG_CRC_ERR bits are cleared. To check if the CFG_CRC_ERR bit is
0 for a matching CRC, the matching CRC value should be stored in the SAFETY_CFG_CRC
register. Then the CFG_CRC_EN bit must be cleared to 0 and set again to 1 which reruns
the CRC on the configuration registers, resulting in the CFG_CRC_ERR bit being 0.

This works as expected when the system is brought up from a power down state.  When EE_CRC_EN is set the EE_CRC_ERR flag is immediately set. After about 800uS the EE_CRC_ERR and CFG_CRC_ERR flags are cleared as expected. The code exits normally by following the process listed in the note.

When the system is cycled using the IGN pin, with POST_RUN_RST=1 and IGN_PWRL=1, the same code fails. The CFG_CRC_EN process works as expected by setting the CFG_CRC_ERR flag. When the EE_CRC_CHK is set the EE_CRC_ERR bit never sets to indicate the check is in progress. After the ~800uS the process does not clear the CFG_CRC_ERR flag leaving the software stalled waiting for CFG_CRC_ERR to clear indicating a successful  EE_CRC test completion.

I'm assuming some register value or internal process is not reseting the same under IGN vs power up but cannot pinpoint it. Figure 5-16 Device Controller State Diagram indicates that both of these paths (IGN and power up) should result in the power supply entering the RESET state, which I would assume would reset ALL the internal values independent of what initiated the reset.

Can you explain what might be different between the two reset initiators (power up and IGN recrank) and how that might be affecting the EE_CRC_EN response?

Thanks

  • 0
    TI__Mastermind 20590 points

    Hi Allen,

    There is a difference in which state re-initialized which registers in the TPS65381A-Q1.  Think of RESET state more as a state to reset the MCU due to detected faults needing a reset the MCU instead of faults impacting the TPS65381A-Q1 and needing to fully reset the TPS65281A-Q1.  To reset the TPS65381A-Q1 fully a NPOR event is needed. 

    The datasheet lists which registers are re-initialized by which event or state transition.  In section 5.5.3.x for each register, under the register name is a line titled "Initialization source:"   This line will include NPOR (power on reset of the TPS65381A-Q1), RESET state or post LBIST re-initialization (LBIST is run from RESET state assuming Auto_BIST_DIS = 0, default for this bit).  This section also lets you know if the register is read only, read/write and if the register is lock against write updates outside of DIAGNOSTIC state and how the SW_LOCK command impacts the register. 

    Section 5.4.26 explains the Power on Reset (NPOR) and its sources.  A summary of the registers that are reinitialized by LBIST (and thus RESET state if Auto_BIST_DIS = 0) is also in section 5.5.3. 

    So most likely the reason the code isn't working on the case where POST_RUN_RST is used with a transition through RESET state is that the software has already configured some registers in the TPS65381A-Q1 that are not re-initialized by the LBIST run triggered on the RESET to DIANGOSTIC state transition.  These registers with the configurations will impact the CRC value the TPS65381A-Q1 calculates and it will not match what a calculated NPOR initialized device would calculate so the CRC fails.

    Hopefully this helps you track down the difference with these registers since they initialize differently between post-LBIST re-initialization and NPOR initialization.

    Please let u know if you have further questions.

    Best Regards,

    Scott 

  • 0 in reply to Scott Monroe
    Prodigy 150 points
    Scott,

    Thanks very much for the quick reply. I had missed the "Initialization source" listed at the top of each register description. Once I saw that, the problem was easy to fix. The EE_CRC_CHK flag in the SAFETY_BIST_CTRL is NOT reset by a re-crank on the IGN pin but is by the NPOR. The code was leaving this bit set after completing the EEPROM CRC check. After a IGN reset, this was still set so when the program "Set it again" the value did not toggle and the EEPROM CRC check does not restart. this hung the system waiting for the EEPROM CRC check to complete. The simple fix is to simply clear the EE_CRC_CHK flag before setting it again. If an IGN reset occurs part way through the EEPROM CRC check, the flag can be left hanging in the set mode. By clearing EE_CRC_CHK before running the test, this rare, but possible hangup point can be avoided.

    The initialization program now completes correctly independent of the RESET source.

    Thanks!

    Allen