LM5105: Do the maths with higher frequencies

Hello Marcel,
Thank you for considering the LM5105 for your design and your interest in TI half bridge drivers. I am an applications engineer supporting this device and will work to address your concerns.

In reviewing the datasheet in the switching parameters, I see that the 1st four listing show propagation delay with various RDT values, none or grounded, 10K and 100K. The propagation delays are 100ns nominal with 10 K resistance, but are 26ns with the pin grounded. The dead time, DT1 and DT2 between the signals is 80ns with RDT set at 10K. So there is some loss in dead time due to the inherent propagation delay of the part.
This does not explain the comment that you see no dead time however.

Can you provide details of your design to help us understand the issue? Confirm the operating frequency of 500kHz and the expected duty cycle range of the HO output. Is the 95% the maximum duty cycle?

Does the driver work as expected with a duty cycle lower than 95% where there will some expected on time on the LO output?
Can you provide scope plots of the IN, LO, HO, and HS with various operating duty cycles? One showing the condition you mention at 95%, and another with lower duty cycle where the LO has time to switch. Since there is 100ns between each edge, record at 75% duty cycle to ensure there should be clear dead time and LO on time.

Regards
Richard Herring

Hi Marcel,

Thanks for asking about LM5101 and welcome to e2e. Im an apps engineer with this device and will help you out.

Since the FETs are blown, the driver might be bad. Does this issue go away when replacing the part? If so, then the device may be damaged and DT is not the root cause.

There are a number of ways why the shoot through could be happening. Firstly, since this behavior is not supposed to happen, there should always be a DT between HO/LO. For this reason, I would like to see scopeshots of HO-HS,LO-GND, RDT,VDD. (to confirm this is the issue) can you also show me your schematic for LM5105 and FETs.

As a secondary possibility, I also notice that the datasheet example is similar to your parameters however they use 100kHz@95% Fsw rather than 500kHz@95%. This could limit minimum LO on time preventing the HB-HS bootstrap cap from fully charging and thereby driving the FET at a voltage less than VDD possibly in the linear region.

Thanks,

Sorry for answering that late, but I had a quite stressful week.

We also did a little bit of examination and found out the following. There is a normal dead time if the pwm is between 5 to 90 %. But if you reach about 94% the dead time suddenly disappears.

Here you see the gate signals. Blue is bottom, yellow is high side. They are a little bit round because we inserted a 3.9 Ohms resistor parallel with a diode to rescue our system.

In the first picture everything is fine, dead time is there, all good. about 92% PWM

in the second picture we rose up to 94% and not only the dead time between high(down) and low(up) disappears, also the wide of the highside gate grows again.

so far we came now. We will investigate further, but perhaps you can clear up that problem a little bit.

500kHz frequency confirmed

max 95% Duty cycle confirmed

it work fine between 5% to 92%

additional point:

if you go to the LM5105 homepage they tell it has 10ns rise and fall and 2A peak current, but if you look in the datasheet it's only 15ns and 1.8A peak current rise and 1.6A peak current fall. prop delay instead is written to 35ns on the hp but 26ns typ in the datasheet.

www.ti.com/.../LM5105

www.ti.com/.../lm5105.pdf

Hi Marcel,

Thanks for your update, no worries, take your time.

With 500kHz input frequency, and while increasing the LO duty cycle to 95%, and therefore decreasing HO minimum on time LM5105 is sacrificing LO deadtime (or the time shown in the scope cursors) with a longer HO on time producing the affect of minimum HO. I would like to confirm what the inputs are doing during this.

If this is a buck... this may be from volt*second balance overcoming minimum system DT + HO on time. Without considering deadtime a half bridge at 5% HO on time (95% dc) @ 500kHz yields 100ns (or 5%period) or the minimum time the converter needs to switch the highside to produce the required output. Add 100ns for HO deadtime and max duty cycle becomes 90%. Any more LO on time after 90% will increase the falling ripple too much requiring the need to have a greater positive going ripple meaning more on time would be needed for the volt*second balance of the inductor.

-can you scope the voltage on RDT during this time as well? if too much noise is on RDT a bypass cap may be needed.
-what diode are you referring to the boot diode or anti parallel gate turn off diode?
-thanks for letting us know about the hp error. the datasheet is the correct one. I will fix this to the correct peak and typical values.

Thanks,