A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
the /reset output shall go down to 0V as fast as possible when VDD is below the nominal value. But when VDD is going above the threshold value the /reset output shall wait the delay time before going high. Does the chip work like this in your application?
Before VDD reaches 1.1V, the RESET output is undefined and can ramp as high as 0.2V while VDD is powering up. Is this what you see? Please provide oscilloscope captures to show the issue. Thanks!
I don't see any issue. This is a push-pull device meaning when VDD is above the VIT threshold, RESET pulls high to VDD. As you increase VDD, the RESET "high" voltage will continue to increase also since RESET = VDD when VDD > VIT. I can see the moment when RESET pulls high right after the initial slope on RESET signal.
the TPS3802 provides a /RESET signal, not a RESET. So, during power-on, after VDD has reached 1.1V the /RESET signal should go to 0V and stay there for 380ms before going high.
I affirmed that condition to my customer.
There were the potential that reset terminal of CPU was high logic because latch-up occured as power on sequence to CPU.
