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BQ76940: circuit design and spec problems

Part Number: BQ76940
Other Parts Discussed in Thread: CSD13381F4, TIDA-00792, TIDA-00449

Hi Engineer,

I would like to confirm some designs in TI’s application reports.

1. I would like to confirm that the N-MOS is feasible to be used as an external balancing MOSFET with BQ76940 (14S batteries)
(ref: http://www.ti.com/lit/df/tidrqy7/tidrqy7.pdf) Another application report also states that N-channel balance FETs can be used and may be preferred.(as discussed in http://e2e.ti.com/support/power_management/battery_management/f/1002/t/673355, and Application Report http://www.ti.com/lit/an/slua749a/slua749a.pdf).

2. If N-MOS are applicable, I would need some advice on which N-MOSFET to use with lower Leakage Current. Here are my requirements. My batteries have 4.2 V max and 2 V min, total maximum voltage 60.2 V(14S), the balancing current would be 16~20mA (I know that CSD13381F4 is one of them. But I think it will be overqualified) and the expected Leakage Current <= 100 nA.

3. I would like to know how to reduce the power dissipation in the source follower as shown below without driving too much power dissipation by internal linear regulators. My requirement would be 50 mA ~ 10 mA.

Either adding resistors, choosing the right side to put the diode pair as shown below, or choosing the suitable MOSFET (Leakage Current is still an issue.) would be appreciated.

Thanks a lot.

I look forward to your reply!

Best regards,

Matthew Cheng

  • HI,
    Your post has been assigned to one of our BMS experts.
  • Hi Matthew,
    1. Yes, N-channel balancing FETs can be used. Select a suitable FET for your situation. The one in TIDA-00449 and TIDA-00792 has worked well in our tests.
    2. Check with your preferred FET supplier or distributor for options.
    3. The REGOUT is only specified to 20 mA. For higher currents you will likely need an external regulator for the current. You may also want a dc-dc regulator due to the power dissipation of dropping the voltage.
    With the linear regulator to REGSRC, power can be split between 1 or more resistors and the FET. Calculate the voltage drop with ohms law, consider the voltage range of the battery. Consider that at low current there won't be much drop across the resistors. At high current be sure the FET has enough voltage to provide adequate REGSRC for the FET outputs. Resistor in the source follower source will lower REGSRC voltage and the FET output level. Pick something suitable for your system.
  • Hi engineer,

    Thanks for your information!

    I've changed my design as following:

    Total Cell Voltage: 4.3*14 = 60.2 Vmax & 2.2*14 = 30.8 Vmin

    VC5X = 21.5 Vmax & 11 Vmin

    REGOUT: 3.3~2.9V 20 mA

    REGSRC as a voltage input to the external regulator TLV70436: 30 mA (including REGOUT output current)

    Please help me check whether or not the design below would be able to fit my requirement. Thx.

    BTW, the connection of C21 in TIDA-00449, C22 TIDA-00792, and C19 in EVM are filtering capacitors for VC1.

    While C19 in EVM seems to connected to ground directly,

    C21 & C22 both connected to VC0 rather than ground.

    Please also help me figure out this question. Thanks.

    TIDA-00792:

    TIDA-00792:

    Datasheet:

    EVM:

  • Hi User,
    R3 and R227 in the above schematic segment sum to just over 1k. If you draw 50mA through these resistors they will drop about 50V and your regulator will likely have too little input voltage. You may need a switching regulator for efficient power transfer at high current.

    The capacitor for VC1 incorrectly goes to VC0 in TIDA-00449 and TIDA-00792. This has not caused problems in test but the topology in the data sheet is preferred and recommended.