Other Parts Discussed in Thread: TPS3808
Hello,
Using the TPS3808G01DBVR, we have the #RESET output pin 1 pulled up to +3.3V through a 1k resistor. VDD pin 6 and SENSE pin 5 are tied to a +2.5V supply that comes up after the +3.3V rail. on Ct pin 4 we have a 2200pf in parallel with a 1000pf capacitor placed to GND, cumulative of 3200pF or 3.2nF of capacitance to GND that calculates to ~19mS of delay. I see in the datasheet it explains to use no less than a 10k pull-up resistor if #RESET output is connected to a voltage higher than VDD. #RESET out is also connected to the input of a rst signal for cpu which is how we discovered the misbehaving signal in the first place.
Recently we've been experiencing pulse width delays that are erratic that aren't making sense as to what capacitance is applied to Ct pin being 3.2nF (~19ms). I've seen this component in our systems having a delay anywhere between 3 mS on upwards to 4 seconds de-asserting the output on assertion of #MR. I'm wondering if this is related to the parts erratic behavior and attributing the the reliability of the components. Here's the snippet from the datasheet stating the a rule to follow for connections on the output:
"RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET will remain low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pull-up resistor from 10kΩ to 1MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD"
Any help and clarification of this issue would be much appreciated and thanks in advance!
- Jesse L