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TPS3808G01DBVEVM: TPS3808 #RESET output delay erratic

Part Number: TPS3808G01DBVEVM
Other Parts Discussed in Thread: TPS3808

Hello,

Using the TPS3808G01DBVR, we have the #RESET output pin 1 pulled up to +3.3V through a 1k resistor.  VDD pin 6 and SENSE pin 5 are tied to a +2.5V supply that comes up after the +3.3V rail.  on Ct pin 4 we have a 2200pf in parallel with a 1000pf capacitor placed to GND, cumulative of 3200pF or 3.2nF of capacitance to GND that calculates to ~19mS of delay.  I see in the datasheet it explains to use no less than a 10k pull-up resistor if #RESET output is connected to a voltage higher than VDD.  #RESET out is also connected to the input of a rst signal for cpu which is how we discovered the misbehaving signal in the first place.

Recently we've been experiencing pulse width delays that are erratic that aren't making sense as to what capacitance is applied to Ct pin being 3.2nF (~19ms).  I've seen this component in our systems having a delay anywhere between 3 mS on upwards to 4 seconds de-asserting the output on assertion of #MR.  I'm wondering if this is related to the parts erratic behavior and attributing the the reliability of the components.  Here's the snippet from the datasheet stating the a rule to follow for connections on the output:

"RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET will remain low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pull-up resistor from 10kΩ to 1MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD"

Any help and clarification of this issue would be much appreciated and thanks in advance!

- Jesse L

  • Jesse,

    I would like to see an ocilloscope capture, if possible, of VDD, SENSE, /MR, and /RESET so I can see the voltage levels during the transition. I know that when you decrease the pull-up resistor, the VOL value increases. This means the /RESET output can be higher than you expect when in the "low" logic state. I would double-check the signal integrity and how you are measuring it.

    Also, during the testing, try removing all connections from /RESET and re-measuring the delay to see if the connection to the CPU is significantly altering the delay due to pull-up or pull-down resistance on the TPS3808 /RESET line.

    Lastly, have you used known to be good devices? Have you seen this issue on every device, every time you try? Or sometimes does the circuit work as expected? If this a new application, or an application that was previously working?

    I will try to help you get this issue resolved ASAP. Thanks!

    -Michael

  • Michael,

    Thanks for the quick feedback, really appreciate it.

    I was asking about the output #RESET pin voltage pull-up to better understand the allowable current for #RESET pin which it looks like min/max of -5/+5 mA in rev K datasheet, and if using a 1k to 3.3V would be detrimental to component health or not. If this would be correlative data that proves to weaken or damage the parts, it would sway a decision to fix many of the applications and use a weaker pull-up here as the datasheet recommends. In terms of VOL in the failing instances of erratic pulse widths, I've seen #RESET to measure no higher than reference gnd 0 volts when it's held low.

    To answer your question about removing the pull-up and checking failure instances, there was a change in all 3 failing samples I had that are no longer failing (at all over many power cycles) which is very different from before only after removing flux paste/excessive conformal coating/and perhaps a chemical stripper around the part in efforts to get some hi-def pictures. There is rework that happens for a change adjacently to the TPS3808 on our application and it's very suspicious as this part is used 2 other times on this same design none of which are seeing no other pulse width failures at the other ref designators. Impedance checks before removing the debri were ok so it doesn't seem like the material removed from all the around the component was metallic in nature. Would Ct pin be this sensitive to say a liquid chemical stripper that perhaps got caught underneath application of coating? I see in the reference design examples for TPS3808 this pin has a nice space around it I'm wondering in efforts to protect it from other stray capacitance? Trying to run a few experiments on this now that have proved to change with the parts behavior pretty drastically.

    Lastly, yes when they were in a failing case (before debri listed above removal) they were varying all other the place pulse width wise in respect to #MR and output #RESET. Now after all this has been removed all 3 samples are measuring consistently every power up at 19mS. If i can get my apps to fail again I will provide screen captures. Do you have an email I could respond to perhaps?

    -Jesse
  • Hi Jesse,

    in section 8.3.4 of datasheet of TPS3808 you will find the following phrase:

    "The pullup resistor should be no smaller than 10 kΩ as a result of the finite impedance of the RESET line."

    The TPS3808 is a low-quiescent current reset chip. Because of this the drain source on-resistance of reset MOSFET is rather high. If your pull-up is too strong the reset output level can rise too much and will decrease the noise margin. As consequence, a bit of ground noise, introduced by ground bounce for instance, can make any circuitry connected to the reset line of TPS3808 misinterpret this reset signal. As result of this other unwanted togglings can occur which can now the TPS3808 confuse. So, a non valid reset output signal can cause a cascade effect, making the TPS3808 look defective.

    Other question: Are you sure that the reset input of your µC is a pure input? Is there any circuitry which can also drive the reset line?

    Kai
  • Jesse,

    To answer your question:

     "Would Ct pin be this sensitive to say a liquid chemical stripper that perhaps got caught underneath application of coating? I see in the reference design examples for TPS3808 this pin has a nice space around it I'm wondering in efforts to protect it from other stray capacitance?"

    Yes, the TPS3808 can detect capacitance as low as 100pF. The CT pin charges the capacitance on this pin using an internal current source until the internal threshold is reached, so adding additional capacitance will extend the delay, and if somehow the capacitance drops below 100pF, the TPS3808 will enter a fixed delay configuration of 20ms.

    Because the same devices are no longer failing after the removal, I am certain the issue is a board or layout issue.

    And to Kai's point, a 10k pull-up is recommended, but so long as the RESET current is within ABS MAX spec, there will be no device damage and the device should still function correctly. This means that you can reduce your pull-up resistor if you are not pulling up to the max voltage, so long as the RESET current is less than 5mA. I don't think the pull-up resistor or pull-up voltage is the issue but I think the CT pin has something on it causing the delay to fluctuate.

    If any additional support is needed, feel free to email me at michaeldesando@ti.com

    -Michael

  • Thanks Michael and Kai for the help with the usage of the part.  I'm attributing the components not working as a result of having soldering debri underneath and around the components (specifically the sensitive Ct pin).

    -Jesse