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UCD9222: FLT Cause UCD9222 and UCD7242 POWER RESET

Part Number: UCD9222
Other Parts Discussed in Thread: UCD7242, USB-TO-GPIO


I have a board with two DSP(C6678). Each one has dedicate one UCD9222 and one UCD7242 to provide Core(rail #1: 1.1V) voltage and fix(rail #2: 1.0V) voltage.

When I enable only One DSP Core and Fix voltage, both 2 DSP UCD9222 and UCD7242 can works fine.

But when I enable 2 at the same time. the DSP2 UCD9222 and UCD7242 will trig FLT and reset, and retry then reset again. Same FPGA Code with DSP1 and DSP2 pin assignment exchanged, the failure one is still DSP2.

The only connection between 2 DSP is the JTAG chain(one JTAG connect, daisy chain 2 DSP) as below:

Any possible that cause such symptom? Please help.

Thanks a lot.

  • Hi,

    A couple things I noticed

    1)  nTRST is pulled high on both controllers, datasheet indicates that this pin should be pulled low with a 10K ohm resistor.

    2)  Is the +DSP_1.8VL bias actually 1.8V or 3.3V?

    It looks like each controller comes out to its own JTAG header so I'm confused when you say they are daisy chained.  Do you mean they are written in parallel from the same cable or is the cable wired to daisy chain the two controllers?

    Can you perform a file compare between the loaded code and the original project file?  There is a tool for performing this in the Fusion GUI Tools folder, search for Project File Compare Tool, run it while connected to the HW and select Add attached devices (offline or online), it will be an option if you are connected to a device, and then Add Project File to load the original project file.  With the Only Show Differences box checked then it will highlight any variations between the two selections, there will likely be some within the Status values returned which is OK but there should not be any within the configuration.

    Do all the faults that appear in the GUI occur with every power up? If you cleared faults and restarted would all these faults appear?

    The CML faults are not a typical fault condition.


    It would help if you could forward your full power schematic for the UCD9222 and UCD7242 and the project file for the controllers.

    If needed, you may friend me in the E2E which would allow you to PM any information just to me after I accept.

  • Hi, Brad,

    1. Yes, I will correct it to 10K pull-down in next version Schematic. 

    2 . What I mean they are daisy chain in JTAG is that they sahre TMS, TCK and NTRST, the JTAG TDI to DSP1 TDI, DSP1 TDO to DSP2 TDI, DSP2 TDO to JTAG TDO.

    That's traditional JTAG to multi Dvice Circuit.

    BTW, The 1.8V is measured about 1.793V

    3. Today I tried erase the DSP1 IBL store in EEPROM. seem the power can perform normally when power up. (did not download IBL before, only DSP1 will load IBL in my previous test)

    Will any DSP setting will cause the second DSP2 1.1v and 1.0v overload?


  • Hi Brad,

    Further more update, when I only enable the DSP2 1.1v and 1.0v power supply, the UCD9222 monitor as below: (Already clear faults and clear logged faults)


    But once I enable the DSP1 UCD9222, The DSP2 UCD9222 voltage and current will fluctuate heavily as below: (Already clear Faults and Clear Logged faults)


    Any possible reason for the DSP1 affects DSP2 UCD9222?


  • As for the error messages shown above, is there another Master (other than the USB-to-GPIO) on the PMBus bus used by the UCD92 controllers?

    It looks like there may be collision between two masters which could cause these error codes.

    If possible isolate the controllers from the other PMBus master while using the USB-to-GPIO adapter.

    The FLT error code is likely due to an overcurrent event on the UCD7242, but could be due to instability of the control loop given that you are also seeing OV and UV faults as well.

    Can you provide the configuration files (.xml) for both controllers and schematics for these power components, you can use the PM connection we setup if you would not like to post them to the E2E.

    I cannot speak to the C6678's loading requirements, not my area of expertise, I believe this is highly dependent on the coding loaded onto the DSP. You could post to the Processor E2E for assistance with calculating the expected power requirements of the DSP.  Since DSP2 starts and runs by itself I would not think that it is a loading issue unless having DSP1 running somehow increases the loading on DSP2.

    Is it possible to unload the coding from DSP2 so that its loading requirements would be reduced or to disconnect the UCD9222 and UCD7242 from the DSP to see how it operates on its own.

    Have you looked into the PCB layout to rule out any issues there?


  • Hi brad,Hi Brad,
    Glad to get your reply.
    As you guess, I have a MCU to connect to the PMBus to control the UCD9222. So I will ignore the CML error first.
    Please note that I have PM you and shared you the .xml and schematic.
    If possible, would you please share me your Email for efficient communication.

    Thanks a lot.