Other Parts Discussed in Thread: SN74AHCT594,
Hello,
I want to cascade as many as 8 SN74AHCT594 shift registers (for general purpose digital outputs) and 3 TLC5916 shift registers on the same serial interface. Serial Clock rate should be between 100kHz and 1 MHz. Is that generally possible ? I didn't find much information on the nature of the Serial output (SDO) of the TLC5916.
1) Does the SDO on the TLC5916 behave the same as the Serial output pin of the SN74AHCT594 ? I.e. the highest bit is shifted into the SDO once a serial CLK is applied ?
2) Is there any preference as to put the TLC5916 or the SN74AHCT594 first? I think the slower TLC5916 should be first to avoid spurious serial inputs when the fast shift registers write into the slow inputs.
3) I am aware that the enable pin on the TLC5916 has an inverse logic than the clear pins of the SN74AHCT594. I will need to buffer the CLK signals anyways, so I can generate an inverse logic enable, too. But is there anything else important to consider when using mixed shift registers?
Best regards and thanks in advance!
ps: maybe that question fits better to the Logic forum ?