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TLC5916: cascading several SN74AHCT594 and TLC5916

Part Number: TLC5916
Other Parts Discussed in Thread: SN74AHCT594,

Hello,

I want to cascade as many as 8 SN74AHCT594 shift registers (for general purpose digital outputs) and 3 TLC5916 shift registers on the same serial interface. Serial Clock rate should be between 100kHz and 1 MHz. Is that generally possible ? I didn't find much information on the nature of the Serial output (SDO) of the TLC5916.

1) Does the SDO on the TLC5916 behave the same as the Serial output pin of the SN74AHCT594 ? I.e. the highest bit is shifted into the SDO once a serial CLK is applied ?

2) Is there any preference as to put the TLC5916 or the SN74AHCT594 first? I think the slower TLC5916 should be first to avoid spurious serial inputs when the fast shift registers write into the slow inputs.

3) I am aware that the enable pin on the TLC5916 has an inverse logic than the clear pins of the SN74AHCT594. I will need to buffer the CLK signals anyways, so I can generate an inverse logic enable, too. But is there anything else important to consider when using mixed shift registers?

Best regards and thanks in advance!

ps: maybe that question fits better to the Logic forum ?

  • Hi, Tobias,

    1) Yes, the highest bit is shifted first.
    2) TLC5916 should be in the first to make sure the hold time is met.
    3) You can adjust the signals to meet both these two devices. The most important thing is to meet the timing requirement for both devices to avoid the unexpected data missing. The minimum propagation delay time of TLC5916 is 8ns, which is OK for the minimum hold time 2ns of SN74AHCT594.

    Please help to click "Resolve" if the problem is solved.

    Thanks.
    Regards,
    Kenneth