This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS62821: Quiescent Current and Threshold on 100% Duty Cycle Mode

Part Number: TPS62821

Hi team,

I have a couple questions with a customer looking to use this device in a low Vin, low load setting. In the particular low power setting, the input voltage can be as low as 3.3V with a load of 15uA, with the desired output voltage at 3.3V.

First of all, what's the threshold voltage difference between the input and output voltage for the device to enter 100% mode where the low-side switch is off? I see section 8.4.3 mentioning the minimum Vin, but what would be the max before going into PSM mode? Would load current matter here and if so what would it be with the load at 15uA?

Secondly, just want to confirm the quiescent current at 100% duty cycle mode.  The electrical characteristics table on page 5 in section 7.5 mentions that Iq typ is 4uA and max is 10uA.  This would be the same at all loads while the device is operating in 100% duty cycle right? I see graphs such as Figure 8 showing a curve with the efficiency lower at lighter loads (black line), is that just because of the ratio of the quiescent current and load current?

Thanks for the help and best regards,

Jerry

  • Hello Jerry,

    It's my pleasure to help you.

    To find the Vi-Vout value for 100% mode operation, just bring the Vout term to the right member of equation (3) at section 8.4.3 of the DS. You'll find it depends on the load current and is: Iout+(RDS_on + DCR_L ).

    The Vin(min) value specified in the same section is the value below which you won't have anymore Vout regulation because of the 100% mode. To exit 100% mode, the error amplifier must detect the Vout change due to Vin rise, and turn on the low side. This value is subject to many internal variables and external as well, and can't be predicted on a static base. Since the error amplifier and the compensation network are involved, this value depends also on the dinamics of Vin and the whole system.

    "Would load current matter here and if so what would it be with the load at 15uA?" I am sorry, I don't get the question.

    The quiescent current does not depend on the desired load current, but on the mode of operation, so if one stays in 100% mode, the Iq will stay the same independently from the load.

    At light load, the Power consumed by the constant Iq drawn by Vin weights more in the efficiency calculation, hence the drop of efficiency, so yes it depends on the Iq/Iload ratio.
  • Hi Emmanuel,

    Thanks for the help.  I have a follow up question after looking a bit closer in Figure 8 of the datasheet:

    Looking at the point where the 3.3V line (100% mode) crosses 1mA on the x axis, the efficiency is 80%. Losses from resistance are going to be very small at 1mA, so I would imagine a rough estimate would be to assume most of the losses are based on quiescent current. If the Iq is 10uA max like the datasheet says, the efficiency should be around 99%, not 80%. 80% efficiency implies there's a current of ~200uA. What are other factors causing of the drop in efficiency?

    Thanks for the help and best,

    Jerry

  • Hello Jerry,

    The value quiescent current you have to consider in this case is not the 10uA you find in the datasheet, because the conditions are not same. The 10uA are referred to a non switching situation, which means both high side and low side fets are turned off. This situation, combined with the Iload=0 condition, basically refers to PSM operation.

    In 100% mode the high side is constantly on, so the quiescent current has a quota related to the current needed to refresh the gate of the high side and keeping it in on-state with a certain Rds_on. Hence the lower efficiency you have noticed is explained.