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UCC27524: Device not switching from 3.3V FPGA I/O Logic

Joseph Lyons
Prodigy 10 points
Part Number: UCC27524
Other Parts Discussed in Thread: UC2709

Hi All,

So I am developing a new design for an application and previously had great success with the UC2709 driver.  Now, trying to do my due dilligence for obsolence I quickly realized this part was designed a long time ago and it would behoove me to try out new drivers.  This led me to to try out the UCC27524 non inverting gate driver.  I don't have a shcematic for you but let me be as despcriptive as I can be.

I am powering the DIP version of this part on a small breadboard with 15V from a benchtop power supply connected to pin 6 and ground connected to pin 3.  I am using an Artix-7 CMOD35T development board to drive one(eventually two, 90 out of phase) I/O with 3.3V TTL pulses at 2MHz.  I have a common ground connection between the device, FPGA, and power supply.

Some obervations:

  • First, with no inputs the device draws 1mA.
  • When I run the FPGA routine, and have one output connected to pin 2(INA) the device does not draw any more current.  I verified with an oscilloscope that the signal from the FPGA is okay.  The output from OUTA is nothing at all.
  • The same result is obtained when I use a benchtop function generator with 3.3V or 5.5V TTL pulses as well.

I ordered a batch of 10 of these from Digikey and have frustratingly had no success.  With the UC2709 I had no issues with this setup.  I also realize that perhaps I may benefit from using decoupling capacitors but this does not seem to explain the behavior I'm seeing.

Is it possible I have a bad batch of devices or I am making a mistake with my test setup?  Let me know if i can provide details that will help me to resolve my issue.  Thank you!

  • 0
    TI__Expert 3355 points
    Hi Joseph,

    I'm an applications engineer in the High Power Drivers group and can help with your question.

    I highly recommend adding some decoupling capacitance from VDD (pin 6) to GND (pin 3) of at least 0.1uF, in parallel with >1uF bulk cap. The driver will still pull some transient current to switch the output CMOS stages, which can become significant, especially at 2MHz. The lack of decoupling capacitors could cause the driver to pull VDD under the UVLO limit, which disables the outputs entirely.

    It also seems one of the biggest differences migrating to this driver is the inclusion of enable pins for both outputs. These are active high inputs which are internally pulled up. This would mean that you could normally leave them floating and both inputs would be active. However, without decoupling caps, these inputs could be pulled low when the outputs try and switch, which would disable the outputs entirely until pin is pulled up again. I would recommend pulling these inputs above their input thresholds externally when doing this breadboard testing.

    If these recommendations do not work, could you provide a schematic of your current setup (drawn and scanned in high resolution work fine), along with screen shots of INA/INB, OUTA/OUTB and VDD to see what they look like?

    If this helped resolve your issue, could you please press the green button?

    Thanks and best regards,

    John