CSD97396Q4M: Power loss at higher output voltages .

Hi user5349740,

Thanks for your question!

The CSD97396Q4M is optimized for low duty cycle applications, but can still be used with high output voltages provided you stay within the recommended operating conditions.  In particluar, I would pay attention to the VIN and duty cycle specification.  You'll also need to pay attention to the maximum power dissipation.  The maximum current at which you will be able to operate will be limited by the power dissipation at such a high output voltage.  Finally, you will want to consider whether you need to start up into a pre-biased load.  Prior to startup, the boot strap capacitor cannot charge when the output is high unless the low side FET is turned on (PWM low).  This will prevent the high side from being able to switch until the boot strap capacitor is charged.  As long as you take care with the details, the device should work. 

Regarding estimating the power dissipation, the power loss vs. Vout curve is linear and can be extended that way.  But be sure to adjust your other parameters using the curves provided in the datasheet as well to get the best estimate of power loss in your application.

Best Regards,

Evan Reutzel    

Hi user5349740,

As you can see on the datasheet, we do not recommend operating above 85% duty cycle.  The reason for this is that there is a minimum high side off time that is enforced by the driver of ~150ns.  If you are operating a low enough frequency, you may be able to operate at higher duty cycles, but we cannot guarantee the performance of the part when you operate outside our recommended operating conditions. 

Regarding extending the power loss vs. inductance curve...there are several ways you can do this depending on the accuracy you are trying to achieve.  The most accurate method would be to take some points from the curve provided and use a tool like Excel to curve fit and extend the curve.  However, from looking at the curve it is clear that the drop in power loss is saturating as the inductance gets higher, so you could simply estimate it or you could use a conservative estimate by using the power loss at 1uH (where the curve ends).  This will over estimate the power loss a bit, but since the power loss is going to be dominated by the higher output voltage in your design, this probably won't be a significant source of error in the power loss estimate.

Best Regards,

Evan   

Hi user5349740,

I've put together an example spreadsheet of how this can be done.  I've done it two different ways.  If I just try to best fit the data directly, the power formula works best, but still isn't very accurate.  So instead, I took advantage of the fact that the power loss is approximately proportional to the inverse of inductance.  Then I can get a linear relationship between power loss and 1/L.  This yields a more realistic value for power loss.  The estimate is still probably a little aggressive since the real power loss equation is more complex than the simple relationship above, but it should give you a reasonable estimate.

  Power Loss vs Inductance Example.xlsx

Best Regards,

Evan

Hi user5349740,

Unfortunately the data you are requesting is proprietary and cannot be shared.  The power loss curves accurately represent the power loss in the device including the package parasitics.

Regards,

Evan