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TPS43351-Q1: Could this non-linear behavior be related to the COMP pin clamp?

Part Number: TPS43351-Q1

Dear E2E,

     I have designed a PCB with two TPS43351Q's on board, so a total of four outputs. Three of the outputs look fine when responding to load transients, but one of them stops switching for a short period when I apply a load transient.

Ch.1 = COMP pin, Ch.3 = Output current, Ch.4 = Switch node of affected output

The conditions are as follows: VIN = 13.8V, Vout = 9.0V. Maximum output current is 4A. fsw = 350 kHz, SYNC forced to always CCM. Spread spectrum ON.

Here are some plots showing the load transient respond together with the AC-coupled output voltage:

You can see that sometimes the response is correct - bandwidth is a bit low, but PM is good. Since even forced CCM sometimes still has a mode boundary of sorts, here's a plot with output current going from 1A to 3A:

In steady state, the sensed current signal looks fine to me, both the waveform and the amplitude:

This is for no-load, with a low-inductance test fixture placed across the current sense resistor

And again but for the maximum output current of 4A. I used single trigger because the spread spectrum can make the plot "fuzzy".

According to my network analyzer, the control loop is a bit slow, but perfectly stable up to 3A

This is the complete loop at no load.

And again for a 3A load.

But at 4A the network analyzer gives nonsense:

At 4A the output voltage drops more than it should, it falls to about 8.1V, but it also appears that the control loop is not in control. I read in the datasheet that there's a COMP pin clamp, but it's not clear to me what the clamp voltages are. A discontinuity is visible in my very first scope capture at around 1.58V. Gives the high duty cycle in steady state, this seems to be the most likely reason.

     I'm attaching a schematic in PDF format. Not shown in the schematic are the bulk input caps and input filter. I've checked the input voltage and the VREG pn voltage and both and nice and stable during load transient operation.

     In conclusion, I'd like to keep this output in linear operation over the full range of load current. Can you help?


Chris18-1006 Vout 2 and 5 v4.pdf

  • Hi Chris,
    Thanks a lot for using TI devices! Your question has been assigned to the expert of the device; since the expert usually comes and leaves very early, and it's Friday today, coming Monday is a holiday, so, you can expect to get answer next Tuesday.
    Thanks again and wish you a nice long weekend!
  • Hi Chris,

    Gordon was off today as well, you should expect a response tomorrow.
  • Chris,
    Sorry for the delay, I hope it has not been to much of an inconvenience.

    I am not sure that I understand your PID loop plots. Typically we look for the -180 deg phase crossing to establish the Phase margin, and since you never cross this point in you plots, I'm not sure that I can use them.
    I ran your data for the COMP pin and I am getting very different values. Using your COMP values you are getting a UGB(Unity Gain Bandwidth) of 7.4kHz. This gives you a Zero at 0.3kHz and a second pole around 21.6kHz. We typically suggest a UBG of about 1/10th the switching frequency. That would put you at about 35kHz. This will speed up your response in the feedback loop. The Zero should also be 1/10th the UGB and the second pole should be fsw/2 at around 175kHz.

    Let's try setting the UGB to 35kHz
    RCOMP = 52k
    CCOMP = 1nF
    CCOMP2 = 18pF

    UGB = 34.8kHz
    Zero = 3.1kHz
    Second Pole = 173kHz

    Everything else looks pretty good.
    FYI: Verify that your inductor is not close to saturation at the peak switching currents. You will need a lot of head room as the inductance will drop at high temperatures. This can cause saturation when your design gets warm.

    Let me know how this works for you.
  • Chris,
    I found a definition on how to use your PID loop plots. You have a gain Margin of 6db and a Phase Margin of about -12deg. (If I am reading this correctly) The chip designers have said this IC needs a Gain Margin of greater than 10db and a Phase Margin of greater than -30deg (> -45 is better). This coincides with the UGB frequency that needs to be at least 1/10th fsw. Increasing the UGB frequency should increase the stability of your loop. As your Phase Margin approaches 0deg the circuit will begin to oscillate, and minor load steps or changes can then cause periods of instability when the Phase Margin gets close to 0deg.
  • Hi Gordon,

         Thanks for the detailed response. I should have explained that my network analyzer add 180º to the phase of the plots so that phase margin can be read directly. So, the phase margins are all 70º or above - very stable, but slow. I'll try increasing the loop bandwidth up to around 35 kHz and report back. My MathCAD worksheet says this is possible with good phase margin.

         All the help is much appreciated,


  • Chris,
    That makes sense. Then your Phase Margin is very good. However, your Gain Margin at 0db, may be your problem. I always target 10db margin because at 0db your circuit will oscillate.

    I look forward to hearing about your results.
  • Hi Gordon,

         My turn to apologize - I wrote you just before taking two weeks of vacation, and today was the first day I could try some new control loop compensation values. Unfortunately, nothing has worked so far. I started with new values that would set the GBW to around 30 kHz according to a small signal model based upon my guesses as to the internals of the IC, together with adjustments made after looking at the actual power stage gain/phase plots. Those were: RCOMP = 48.7 kohm, CCOMP = 10 nF and CCOMP2 = 150 pF. Those values doubled the GBW from before, to a range of 10 kHz to 15 kHz depending upon the load current.

    This is at no-load, VIN is always 13.8VDC. GBW is 15 kHz and the gain margin at zero phase is about 24 dB. The highest load I can draw and still get a meaningful Bode plot is 3A:

    At 3A both phase and gain margins look fine to me.But the load regulation is poor and the transient response looks the same as before:

    Ch.1 = Vout AC cooupled, Ch.3 = Iout moving from 1A to 3A and back

    I didn't capture the switch node, but synchronous switching stops during the time that Vout takes those large dips. You can also see that the amplitude and duration of the large dips varies quite a bit. Finally, you can see that the system actually does return to the type of response I would expect in many cycles - that's the point where synchronous switching resumes.

    Since the BW is a third of what you recommended, I put the CCOMP and CCOMP2 values you suggested in (CCOMP = 1 nF and CCOMP2 = 18 pF). I left RCOMP = 48.7 kohm

    This plot is for no-load.

    This plot is for a 3A load. I suspect that the larger amplitude, low frequency injection currents are pushing the system to stop switching, hence the non-linearity up to about 1 kHz. Phase margin is better but the gain margin is worse. And the non-linear transient response is unchanged:

    Actually, it seems a little bit worse - it seems to take longer for switching to resume.

    I'm not sure why the GBW doesn't get to 30 kHz - is it possible that the Gm amp is running out of bandwidth?

    With both of the new compensation schemes my network analyzer was unable to make any linear plots when the load was 4A. In both cases Vout dropped from 8.7V at no-load to around 8.2V at 4A.

    I'm back to suspecting that the COMP pin hits a threshold and stops the switching.



  • Chris,
    I need to look this over. Can you send me a schematic and some what of a layout for this design. You can send them off line to me directly if you wish.
  • Chris,
    Try something for me please, The CBB Boot Strap capacitor, C28. Please change this value to 0.1uf and run your test again. I would like to see the results.
  • Hi Gordon,

          Here are two plots where C28 has been changed to 100 nF, 0603, X7R, 50V:

     Hi Gordon,

    Ch.1 = deltaVo, Ch.3 = Io, Ch.4 = switch node

    This made things worse - the dips are about twice as deep. You can see that the switch node waveform changes:

    Ch.1 = CBB pin WRT GND, Ch.3 = Io, Ch.4 = switch node, Math = Vcbb - Vsw

    This plot shows that the differential voltage across C28 is relatively steady, but it does also look like the high side FET turns off too early. In fact, with only 100 nF I saw similar distortion of the switch node even in steady state with a load of only 1A.

    Just to see, I then put 470 nF on top of the 100 nF in position C28, almost tripling the bootstrap capacitance:

    It looks better but still not resolved.



  • Chris,
    That's what I was hoping would happen. Now change it to 1uf. You are saturating the Bootstrap capacitor. This is the limit you are seeing.

    My calculations say that a 680nf is the correct value, but you would have a problem with low input voltages near the drop out point. So a 1uf cap should take care of that.
  • Hi Gordon,

          I replaced C28 with a 1uF, 0603, 50V, X7R cap - but I don't see any real improvement over the previous test where C28 = 100 nF +470 nF:

    Are you sure this iisn't the COMPx pin clamp?



  • Chris,
    No, I am not convinced its not the COMP circuit. The design group says that this part can operate to 11V out and up to 600Khz. They feel that you are not close to the limits.
    I am going back to them and show them your data and images and see if they still feel the same way.

    Let me have a few days, the design group is very busy. I will get you some feedback as fast as I can.
    Thanks for being patient.
  • Chris,

    I have some feedback for you.

    The clamping of the COMP pin happens at high currents due to shorts. If the chosen components support the load current (FETs, inductors (saturation!), sense-resistor), the clamping should not kick in.

    Observing the COMP-pin can help, but be aware that the probe-capacitance affects the compensation.


    Even though he reports that VREG is stable, we recommend a higher decoupling capacitance than 1uF (see design checklist):


    Please have him remove the 0-Ohm resistor from EXTSUP:


    In low power mode, EXTSUP is not used. If it leaves low power mode, it briefly switches VREG input to EXTSUP to sense the voltage on that pin. With the 0 Ohm resistor, it partially discharges the VREG capacitor.


    I do not see the need for the diodes in the gate-drive lines. Please have him remove those.


    Other general issues in creating the gain-phase plots is that

    • the junction boxes have a finite bandwidth supporting the entire frequency spectrum and will have to be swapped (since the plot is one continuous line, it does not appear he did so).

    • The stimulus settings may have to get altered for different frequencies and/or load currents

    However, since the transient response confirms the issue, I would not  consider a improper gain-phase-plot as the cause…

    I am still working with the design group for more feedback. Let me know your thoughts.

  • Hi Gordon,

         Before getting this message, I also began to doubt the stability of VREG, and I ran a test after removing R15, the jumper that connects EXTSUP to the 5,0V output. The result was quite good:

    Ch.1 = deltaVo, Ch.2 = Iout

    There is some irregular behavior for steady state loads > 3.5A - dips in the output voltage that look a bit like the dips in the previous load transient plots I've sent. I'll put C28 back to 220 nF and also try a 4.7 uF cap on VREG to see if that clears up the steady state dips. Nonetheless, this has been very helpful and I'm going to tick the "Issue Resolved Box".

        Many, many thanks!