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Original question:

BQ40Z60: DSG FET protection cannot be cut off, causing MOS FET to burn out (CHG & DSG FET independent path design )

BQ40Z60: DSG FET protection cannot be cut off, causing MOS FET to burn out (CHG & DSG FET independent path design )

JANSON CHEN
Prodigy 250 points
Part Number: BQ40Z60
Other Parts Discussed in Thread: BQ40Z80, BQ40Z50

HI. Terry / Batt

I further observed the effects of the BMS Chip and Charger mode and DSG Gate waveforms, and found that the Chrager action has absolute influence.

I tried several modes of testing. (See the attached file charger modetest results),Whether the Gate uses a Diode or a resistor, this voltage will be affected as the Charger is turned on or off.

These tests may be helpful in analyzing the problem, and attaching the PCB layout of this Project, can you provide suggestions?

Janson

bq40z60 PCB Layout.PDF

CHARGER MODE TEST.pptx

  • 0
    TI__Genius 10830 points
    Hi,
    Sep 3rd is Labor Day in the USA. We will reply when we are back to the office.
  • 0 in reply to David Hien
    TI__Expert 5230 points
    Hi Janson,

    I checked with a colleague on this:

    DSG drives off to HSRN, to have short circuit support, the CHG FET needs a back to back configuration and the charger output, HSRN, needs a discharge load resistor to ground (100k ohm or so). Then in SCD the charger will be turned off, discharging HSRN to ground allowing DSG to turn off.

    You already have a diode in series with CHG and resistor to ground on HRSN. Maybe your HRSN time constant is just way too big. Maybe you can tolerate a 1k resistor on HSRN to ground which should allow discharge to occur a bit faster (like 50 ms).

    Afterthought - it looks like you want to turn off DSG with the charger on. That won't work since the part drives DSG off to HSRN. You can pull DSG low to pack- with an external FET. The 5k gate resistor should keep the DSG FET reverse current from HSRN limited to about 3mA.

    Thanks,

    Terry
  • 0 in reply to -Terry
    Prodigy 250 points

    HI,Terry :

    Thank you for the solution,

    I tried to add a 1K resistor (even down to 500R) between HSRN and PGND according to your suggestion.
    and tested under FET OFF and Charger ON (19V maintenance)
    A small leakage voltage (approximately 1.5-1.8V) is still seen in the DSG FET (VGS), which causes the DSG FET to turn on.

    First I have to confirm if the Bq40z60 can be applied to the design of the split path?
    If it is ok, I have an idea. If the issue is not a hardware design, can it be solved by Memory setting or updating Firmware?
    Eg. When the Bq40z60 detects a discharge mode condition, it forces all loops and controls with the charger to be turned off ....etc.

    BTW, I tried to refer to the EVM design and modified it to the CHG/DSG FET merge path. This leakage problem was solved.It may be that the Body Diode of the DSG FET reduces leakage.

    But this design is not what I need.

    The reason for using FET OFF & Charger mode for testing, Consideration is that when entering the discharge mode, the 19V and Charger are turned off too slowly(or lose the Charger OFF command from CMD), and an Over Load or short circuit may occur at this time, causing the DSG FET to be damaged.

    The only thing I can suspect is that the leakage is directed to the Chip's VCC Pin through the Charger high-side MOS.
    But the ACFET MOS is also turned on, I can't confirm that this theory is correct.(Please refer to the analysis path of the attached file.)

    Another suspicion is that the Charge pump inside the Chip is activated at the same time, with the influence of the DSG PIN driver.
    This theory must also be analyzed from the Chip.

    If you have a better idea, please let me know.

    Janson

    BQ40Z60 Circuit(1).pdf

  • 0 in reply to JANSON CHEN
    TI__Expert 5230 points
    Hi Janson,

    I don't know if this device has been used with a separate CHG and DSG path, so I am not sure it will really work for you. Another suggestion was you could try a 20v vgs nFET, connect the gate to HSRN, source to PACK+ and drain to DSG on the far side of the 5k resistor. Maybe even replace the 5k with 10 or 20k. That will force DSG to PACK+ whenever DSG is off and HSRN has voltage.

    Sorry for not having a definitive solution for you in this configuration. You might also consider switching to a separate charger and gauge+protector, for more flexibility. The bq40z80 is already sampling and near release, it includes support for parallel FET paths.

    Thanks,

    Terry
  • 0 in reply to -Terry
    Prodigy 250 points

    HI,Terry :

    According to the solution you provided and the circuit of the BQ40z50&Bq40z80 located in the DSG FET, after the experiment, I have not solved the situation described previously. (Please refer to the attached file for the 3 circuits of the experiment)
    I also tried to update the Chip Firmware (0_13 => 0_15) and the result is still the same.

    Therefore, I must immediately choose a solution that can match the split path. I need the following information.

    Short-term Solution: Skip the charger function of Bq40z60, plug in a separate charger
    Questions: 1. Does this modification affect the functionality of Chip AFE & Gauge?
                       2. Can I force the charger function of the Chip to be permanently turned off?

    Long-term Solution : Replace BMS Chip (Study BQ40z50 or BQ40Z80)
    Questions: 1. Is there any application data for the Bq40z50 and Bq40Z80 with a split path?
                       2. The Gauge function of these 2 Chips is IT or CEDV Base?

    If you have further experimental information, can you share it with me?
    And And providing the above information.

    Janson

    7823.DSG FET Solution circuit.pptx

  • 0 in reply to JANSON CHEN
    TI__Expert 5230 points
    Hi Janson,

    I've reviewed this case more with others, and the consensus is that the bq40z60 is not likely to work properly for your parallel path configuration. The bq40z50 also won't work properly, the only one that would be hopeful would be the bq40z80. However, I haven't found good test data on this in parallel FET configuration yet, so I don't have anything I can provide on that yet. Note these are all IT-based gauging, none are CEDV.

    Thanks,

    Terry
  • 0 in reply to -Terry
    Prodigy 250 points

    Hi,Terry:

    It is difficult for me to understand that the BQ40Z50&BQ40Z60 cannot be designed as the main reason for the split path. It only provides the design of the split loop, which is too weak.

    However, the Bq40z80 does not have a strong split path application, and this redesigned solution is too risky.

    Can you let me know the theory of Bq40z60&50 that can't be applied to the split path?

    Thanks

    Janson

  • 0 in reply to JANSON CHEN
    TI__Expert 5230 points
    Hi Janson,

    A key issue is that both bq40z50 and bq40z60 were developed with a series FET configuration in mind, so when a significant discharge occurs, the CHG FET will be turned on , and when a significant charge occurs, the DSG FET will be turned on, as part of the body diode protection. This is generally not acceptable in a parallel FET configuration.

    However, one colleague is still surprised that the approach in solution-1 in your ppt (DSG to PACK FET) did not work, do you know why that was not successful?

    Thanks,

    Terry
  • 0 in reply to -Terry
    TI__Genius 10830 points
    hi Janson,
    Is your issue resolved? If so, please close it.
  • 0 in reply to David Hien
    Prodigy 250 points

    HI,David :

    This ISSUE has not been resolved, as the solution discussed earlier with Terry,It can't solve the problem of DSG leakage after Charger starts.
    (Using the DSG/CHG FET OFF state to observe leakage, this is a proven method and does not mean that I need to turn off the CHG&DSG FET in Charge mode. Unless protection occurs in charging mode)

    Currently I have two solutions in progress:
    1. Maintain CHG/DSG split path design, skip the charging function of bq40z60, and plug in the charger. (currently confirmed)

    If this solution 1 can be solved, I hope to change to the Bq40z50 chip, but I can't get the CHG/DSG split path (For 4S) application, or other chip solutions that fit this application.

    2. Evaluate the feasibility of the CHG/DSG merge path for this product application.
    (But this is not what I want, because the discharge current of the product application is very large and will cause space problems)

    Also, in Sep 1, 2018 7:12 PM (first article) I provide PCB Layout , Can you assist with Review?

    Janson

  • 0 in reply to -Terry
    Prodigy 250 points

    HI,Terry :

    Currently I have cancelled the Charger function and replaced the original charger with the external CC-CV Charger.

    During the test, it was found that once the voltage was introduced into the HSRN Pin and it was in the FET OFF mode, it was easy to find that the DSG Gate voltage would increase (about 1-2V).

    This proves that all the problems pointing to the HSRN PIN is the main cause of this issue, but I can't understand that this is the Current Sensor of the charger. Why does it affect the output of the DSG Gate?

    Have you ever done this experiment? Of course you can also add a DC voltage (~16V), you can also see this problem.

    Please refer to the following circuit.

    Janson

  • 0 in reply to -Terry
    Prodigy 250 points

    HI,Terry : Do you have any further analysis on the problems found in the above external chargers?

    Janson

  • 0 in reply to JANSON CHEN
    TI__Expert 5230 points
    Hi Janson,

    Sorry for the delay - I managed to arrange for a designer from the original development team to perform a review of your case on this device, so I have a little feedback from that review. He indicated what you are trying was not how the part was originally designed, and with the internal circuitry being fairly complex, even he cannot be sure from his memory whether this will operate as you would like.

    Do recall that when the DSG FET is turned off by the device, it pulls it to the HSRN pin voltage. If this voltage is not at 0V, then DSG should not be expected to turn off. So in order for the FET to turn off, you need to ensure that HSRN is driven low in this case. This is why we made the earlier suggestion to add a 20V Vgs NFET, connect the gate to HSRN, source to PACK+, drain to DSG on the far side of the 5k resistor (also consider to change the 5k to 10k or 20k), to force DSG to PACK+ whenever DSG is off. He felt this should work, isn't sure why it would not.

    Beyond this, I think we have exhausted our ideas here. As mentioned before, you might consider looking at the bq40z80 for a parallel FET configuration, to see if that will meet your need.

    Thanks,

    Terry