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TPS7B8250EVM: example of heat dissipation characteristic

mayumi.T
Expert 1015 points
Part Number: TPS7B8250EVM
Other Parts Discussed in Thread: TPS7B82-Q1

Hello,

Is there heat dissipation characteristic data on the TPS7B8250EVM board?
(Eg, ILOAD vs surface temperature or junction temperature)


Please also inform me of input / output voltage condition during measurement.

Thank you.

  • 0
    TI__Guru 55940 points

    Hi Mayumi,

    We do not have data on the heat dissipation characteristics of the TPS7B8250EVM.  Rather we provide thermal information for the LDO in the TPS7B82-Q1 datasheet modeled following JEDEC's EIA/JESD51-x series of documents.  This allows all TI linear regulators to be compared thermally to each other as their thermal metrics are modeled in a standardized way.

    The following Application Report discusses how to use this information as a first pass way to understand how the device with behave thermally in your application.  It is important to keep in mind that since layout plays a large factor in thermal performance, your application specific layout will have different metrics.

    Keep in mind that the primary heatsink for TPS7B82-Q1 is the GND plane.  As such, to achieve the best thermal metrics in your application, maximize the GND copper connected to the LDO within your application constraints.

    Very Respectfully,

    Ryan

  • 0 in reply to Ryan Eslinger
    Expert 1015 points
    Hello Ryan,

    Thank you for your reply.
    I understand that there is no measurement data.
    Please let me ask questions about "Semiconductor and IC Package Thermal Metrics" additionally.

    Is (7) - (11) of Table 3 the same as the measurement condition of Ψ jt of TPS 7 B 8250?

    Table 3. ΨJT for Typical 128-pin TQFP Package (1) (2) (3) (4) (5) (6) (7) (8)
    (1) Size, type, pin: 14 mm × 14 mm × 1.1 mm, TQFP, 128
    (2) Die size: 8.4 mm × 8.3 mm
    (3) Die thickness: 0.31 mm for exposed pad; 0.28 mm for non-exposed
    (4) Die pad size: 10.5 mm × 9.2 mm × 0.15 mm
    (5) Die attach impedance: 5.77 ° C - mm 2 / W
    (6) Mold compound thermal conductivity: 0.9 W / m - K
    (7) Ambient temperature: 25 ° C
    (8) Power dissipation: 1 W
    (9) Size: 114.3 mm × 76.2 mm × 1.6 mm
    (10) Thermal vias: 9 × 9 connecting die pad to ground plane (for for 2 s 2 p PCB with exposed pad)
    (11) Type: JEDEC high-k (2s2p) and low-k (1s 0p) as defined in JESD 51-7 and JESD 51-3, respectively

    By the way, are you planning to respond to WEBENCH in the near future?

    Best regards,
    Mayumi,
  • 0 in reply to mayumi.T
    TI__Guru 55940 points
    Hi Mayumi,

    Yes, unless specifically stated, all TI products are modeled as described in the application report on the JEDEC high-k board for the Thermal Information Table.

    We do make every effort to respond to every post in a timely manor; however, it is possible that we did miss a post. Which post are you referring to by "WEBENCH"?

    Very Respectfully,
    Ryan
  • 0 in reply to Ryan Eslinger
    Expert 1015 points
    Hello Ryan,

    Thank you for confirmation.
    For WEBENCH, my question was hard to understand.
    My customers want to do thermal simulation, but TPS 7 B 82 - Q 1 is not registered in the WEBNCH tool.
    Therefore, I wanted to check if there was a corresponding schedule.

    Thank you.
    Mayumi,
  • 0 in reply to mayumi.T
    TI__Guru 55940 points
    Hi Mayumi,

    Due to low utilization of linear regulators in WEBENCH we are no longer adding linear regulators to WEBENCH. The PSPICE models and evaluation modules will continue to be released with new products.

    Very Respectfully,
    Ryan