Dear TI, (but likely Gordon),
In the same circuit used in my previous post, I have two TPS43351-Q1's. One is the master, with its SYNC pin connected to its VREG pin so that it's always in CCM. The Channel 2 low side gate drive output of the Master, pin GB2, is connected to the SYNC pin of the second TPS43351-Q1. They both operate, but their switching frequencies are not synchronized. I have footprints for an R-C low pass filter between GB2 of the Master and SYNC of the slave, but the GB2 waveform is quite clean. The Master has spread spectrum enabled. Could this be preventing the Slave's PLL from locking? I connected a 50% square wave with levels of 0 to 5V at 350 kHz to the Slave's SYNC pin and that worked perfectly. A second thing II'm wondering is whether the SYNC pin needs a 50% square wave - the GB2 output of the Master s not a 50% duty cycle.
Ch.1 = SW1 of Master, Ch.3 = GB2 pin of master and SYNC pin of slave, Ch.4 = SW1 of Slave
This plot shows that the rising edge of GB2/SYNC is not aligned with SW1 of the Slave, whereas they are aligned when the Slave is sync'd to a signal generator.