TPS43060EVM-199: purpose of multiple vias on the input pad of boost inductor L1

Hello Jasper,
I have another question. TPS43060EVM-199 User's Guide (SLVU828A) section 4.1 says "The ground return for the power components are connected to the PGND pin."

However, I cannot see a connection between the source of low-side MOSFET Q2 and PGND in layout figures 19 - 22. Similarly, I can't see the filter capacitors' (C2, C3, C4, etc.) low side connected to PGND. These connections are, however, shown in schematic Fig. 1 (but do not appear to be reflected in layout).

Would you please help clarifying? I am in the middle of layout.

Regards,

Nitish Agrawal

Hi Jasper,

Thank you for your response and your time looking into my question. I should have looked more carefully. A few more related questions, if you don't mind:

1) In our application, we have reduced the inductance to 8uH from the 15uH present on the evaluation board, while the output current is ~3A continuous. This will cause higher peak switching currents through the low side MOSFET and the filter capacitors.
Will a single via (similar to right side one that you referred to) have enough ampacity to carry the higher magnitude switching currents from the power ground panel to the PGND pin trace?

2) I am assuming that the connection between the power ground panel to PGND pin should be as low inductance as possible. Is that correct?

3) How much inductance is allowable between AGND and PGND so that it doesn't affect high frequency switching performance at ~500kHz?
For instance, is it advisable to use an external jumper for this connection?

Kind regards,
Nitish Agrawal

Hi Jasper,

I trust you are well. Would you mind responding to our latest three questions posted on Oct. 11 (repeated below for your convenience):

1) In our application, we have reduced the inductance to 8uH from the 15uH present on the evaluation board, while the output current is ~3A continuous. This will cause higher peak switching currents through the low side MOSFET and the filter capacitors.
Will a single via (similar to right side one that you referred to) have enough ampacity to carry the higher magnitude switching currents from the power ground panel to the PGND pin trace?

2) I am assuming that the connection between the power ground panel to PGND pin should be as low inductance as possible. Is that correct?

3) How much inductance is allowable between AGND and PGND so that it doesn't affect high frequency switching performance at ~500kHz?
For instance, is it advisable to use an external jumper for this connection?

Kind regards,

Nitish Agrawal