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Original question:

UCD9244: Consistent Problem with VOut with UCD9244

UCD9244: Consistent Problem with VOut with UCD9244

Howard Bandell
Intellectual 555 points
Part Number: UCD9244

The compare tool was helpful. The part is tricky to program. We still have a few issues.

We use 2 UCD92444 controllers on the circuit board. One of the controllers has 2 outputs that partially turn on way earlier than programmed..

They .85 V PWM controller's (UCD's 4th PWM output channel) output slowly rises to .3V in 100 milliseconds and then quickly rises to .85 V in < 4 milliseconds. It was NOT supposed to be starting before 100 milliseconds.

THe 1.8V pwm controller output rises to .8V in 150 milliseconds ant THEN rises to 1.8V in a couple of milliseconds. Again WAY early.

This is controlled by channel 1 of the UCD chip.

The other UCD outputs are perfect.

I looked at 2 boards and BOTH did this.

Should I be concerned? What would cause this?

  • 0
    TI__Intellectual 925 points

    Hi Howard,

    Are you seeing a PWM signal being sent to the Channel 4 powerstages during those first 100ms (150ms for Channel 1)?
    What does the intended power sequence look like?

  • 0
    TI__Genius 13700 points

    I suspect this may be related to the kickstart of the rail.

    The controller is programmed with a minimum driver pulse width based on the chosen driver.

    The system calculates where on the programmed soft start ramp the voltage would be with this minimum pulse width.

    After receiving a valid turn on command (auto on, PMBus_Ctrl, Operation command), the controller waits to that time in the ramp then begins pwm pulsing and finishes ramping to the final voltage.

    So you would get a fast rise to an intermediate voltage followed by the programmed ramp to the final voltage.

    If you were to plot back the ramp on the second half of the startup down to 0V, I would expect that the time should be close to the programmed ramp.

     

    This is particularly a problem with large step down ratios, 12V --> <1.0V and is very dependent on the switching frequency.

    See section 5.3 of the following document for additional information.

     

  • 0 in reply to Brad
    Intellectual 555 points

    The output voltage is ramping up (slowly) BEFORE we have asked it to.

  • 0 in reply to Brad
    TI__Genius 13700 points
    Reading your post again, I expand on my response, it still involves the kickstart though.
    You are using a UCD9244, so I expect you may be powering a DSP with it ( or something similar) with multiple biases and these typically have very specific voltage sequencing requirements.
    It sounds like there is back biasing through the DSP to these rails, possibly due to the delay caused by the kickstart.
    You may need to adjust the delays between rails to account for the kickstart and maintain the correct order of biasing the device.

    You can forward the configuration file and additional information if needed.
  • 0 in reply to Brad
    Intellectual 555 points

    It does seem to be leakage. We are using the Keystone 2 chip. We use two pwm controllers, with PWM signals labeled FAR0# and FARM1# The rails with leakage come from FARM1 PWM4 output(.85V) and FARM1 PWM3 output (1.8V). I will attach the config filesPWM Files.zip

  • 0 in reply to Howard Bandell
    TI__Mastermind 24075 points
    Hi Howard,

    We are going to close this post.
    Please let us know if you need more support.

    Thanks
    Qian