TPS57112-Q1: Minimum UVLO Timing for POR

PY (Pengyu) Song

Expert 5860 points

Part Number: TPS57112-Q1
Other Parts Discussed in Thread: TPS54618

Hi team,

What is the minimum UVLO timing (i.e. Vin <2.28V) for TPS57112-Q1 to detect a POR?

over 5 years ago

0 JohnTucker over 5 years ago

TI__Guru**** 191445 points

Hi PengYu,
There is no specified intentional delay, only the internal gate logic delays.

0 PY (Pengyu) Song over 5 years ago in reply to JohnTucker

TI__Expert 5860 points

Dear John,

Thanks. Understand there is no spec on this parameter, but any reference? For instance, if there is a glitch at Vin, what is the minimum timing that can trigger a valid UVLO? Like us, or ns, or ps, or sub-ps range?

0 JohnTucker over 5 years ago in reply to PY (Pengyu) Song

TI__Guru**** 191445 points

PengYu,
Editing this. We think there was some intentional deglitch included in the TPS54618 as well as parts derived from it such as TPS57112-Q1. The deglitch time should be in the order of 1 usec. If I find out otherwise I will update this.

Power management

Power management forum

TPS57112-Q1: Minimum UVLO Timing for POR