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Part Number: EMB1499Q
Other Parts Discussed in Thread: EMB1412

My client's BMS uses the 1499/1428 for active balancing. The 1499's datasheet shows how to delay the 1499's active clamp signal via a CMOS inverter, which then drives the EMB1412 gate driver.  The gate driver then drives the active clamping PMOS through the recommended level shifter. 

My question is, my client's circuit has the PWM_CLP signal tied to the input of the CMOS inverter... BUT it's also tied directly to the gate driver's output!? 

Your datasheet doesn't list the operating ranges for this signal, but merely mentions that it's a "logic" signal (i.e. not a gate driver), and so I'll guess that it's Iol/Ioh characteristics are limited to +/- 50mA.  My understanding of this circuit is that, when the 1499 want's to turn the clamping FET on, it pulls (or attempts to) PWM_CLP low. But since the 1412's output is sitting HIGH, and is rated to source 3A (i.e. a strong pullup), it would appear that the PWM_CLP signal could NOT pull low, and would do so only AFTER it propagated through the delay inverter??

In other words, for the 300-400 ns delay period, you'd essentially have the 12V supply shorted through the 1412's pull-up FET and the 1499's pull-down FET.

Oh, and vice-versa: when the 1499 want's to turn the clamping FET off, it pulls (or attempts to) PWM_CLP high, but since the 1412's output is sitting LOW, and is rated to sink 7A (i.e. a strong pull-down), it would appear that the PWM_CLP signal could NOT pull high until it propagated through the delay inverter.  So for 300-400 ns, you'd essentially have the 12V supply shorted through the 1412's pull-down FET and the 1499's pull-up FET.

The only potential "explanation" I can see is the comment in the datesheet: "The delay network should provide approximately 300ns to 400ns delay to the turn-on transition of the clamp PFET, and minimal delay to the turn-off transition."

This seems wrong to me, but my client says this circuit came directly from TI's original "Cheetah" reference design.

What am I missing?

Thanks in advance.

  • Hi Jeffrey,

    Tying the signal line to the gate driver's output is indeed concerning for the reasons you mentioned. As I am unable to find a TI Design with the name "Cheetah" as mentioned, would you be able to provide the TI Design number that the client is using?

    In the meantime, for using the EMB1499 with a gate driver, we recommend a Schmitt trigger inverter along with isolation of the PWM_CLAMP signal from the 12V zone. Please refer to TIDA-00817 for our active suggested design for such a setup (in particular, this link has the relevant schematic:

    Let me know if this design fits your needs!

  • Thanks Mr. Toledo;

    The "Cheetah" was the original National Semi's R&D/Reference design for active balancing, begun in 2009'ish. My client used it extensively in their BMS. A 2010 Cheetah schematic shows that the 1428/1499 circuitry is essentially equivalent to my client's, the one major exception is that PWM_CLP signal not being tied to the gate driver's output.
    Is there any way of getting the spec's on that signal? The datasheet merely lists it as a "logic" output, but includes no Voh, Ioh, etc.

  • Hi Jeffrey,

    At this time, we are unable to supply the signal specs for this specific device. I apologize for the inconvenience.