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TPS62162: 3.66V output on 3.3V fixed voltage regulator. Have used IC before without problems.

Part Number: TPS62162
Other Parts Discussed in Thread: TPS62163,

I am currently powering the the SAMC21 in dual power supply mode with the 5V TPS62163 and the 3.3V TPS62162, the 5V IC is working fine, however the 3.3V IC is outputting 3.66V(very stable too), which goes above the tolerance of the SD card on my PCB. I am fairly confident it is not my layout since I have used the TPS62162 on a very similar board(no 5V version) and it worked fine. Also another reason I feel like it is not the layout is that the 5v  and 3.3V volt versions of this IC have the exact same recommended layout. 

The rest of the board is working completley fine, even the ICs that are meant for 3.3V are still functioning(maximum rating is much higher). Its just that long term I feel like the board is prone to randomly failures if I do not address this, especially with the SD card. 

My current theories are that is has something to do with the dual voltage configuration of the MCU, but it is very much indicated in the datasheet that this is an intended feature. Also the impedance between the two power rails while off appears to be in the mega ohms, although I did get a ~50kOhm reading a few times.

Possibly the 5V rail, is messing with the feedback of the 3.3V reg.

Another possibility is that it is a bad IC, and I have extra but this also feels improbable. I thought I would check here and see if I could figure out anything before I replace the IC.

Another detail that may be important is that Vin is a 3S lipo. 

Any ideas on what would cause a .36V increase on what should be a fixed output voltage? 

  • HI Jacob,

    Your theory may be possible, I would need to understand the layout and schematic , could you share them?

  • I also realize that this is not the recommended layout, so I want to know if its even possible that my stable output of 3.66V could be due to noise from the lazy grounding and routing, or if I should just try another IC. Also note that there is a ground pour, 3/4 of the layers on this PCB have a ground pour including the top. By lazy grounding I just mean that I did not separate analog ground and power ground. 

  • As you already noticed the layout could be the cause of the DC shift you observe.
    Although there is a ground pour on the top layer (not visible on the picture) the ground connection between C7 and REG3V is too long, it is going through the REG5V ground pin first and then connected to the PGND pin of the REG3V.

    I would recommend to redesign the layout and follow the DS recommendation, especially making the ground loop connection between the input cap and device ground a small as possible. You could rotate C7 180 deg and place it further on the left side so that the ground of C7 in directly connected to the PGND pin of the converter REG3V.
  • Definitely agree that that is a pretty big path, thanks for pointing that out, but wouldn't this cause noise rather than the stable voltage increase I am seeing?

    I will try shortening that path to see if it affects anything, and will definitely change it in a future design, but do you think it is more likely that its grounding or just the IC?
  • The output voltage of the device is tested in production. The variation you measure would be out of specification. So it is very unlikely that the device causes this unless it has been damaged of course. You should be able to verify that by measuring the voltage between AGND and VOS pins directly at the device.
  • Is this layout better, there was no official layout for the fixed versions of this chip. The ground paths have been fixed, and AGND has been separated from PGND in accordance with the datasheet. I also angled both the inductors at 90 degrees from each other, because I thought that that might also cause some bad coupling, is that a possible cause?

    I just recently got around to fixing this problem, so I'm hoping you you still remember this conversation. I actually tested another IC on the same chip and the same error/voltage was present, so it was not the IC. I will be ordering this design again in the next few days, so if you guys could validate this that would amazing to have peace of mind while I wait.

    Also if your fix somehow works, this is the best support forum ever!

  • I will get back to you beginning of next week.
    Meanwhile did you measure "the voltage between AGND and VOS pins directly at the device" on your old layout as Juergen suggested?
  • With that layout, which had the AGND and PGND linked, I pretty much just measured from VOS to GND, which resulted in the same 3.66V. What should I be looking for, should I be doing this with an oscilloscope? Also I tested another IC, which didn't fix it so I know its not that. 

    Ill add some Vias for those pins in the next design for easier testing. 

  • Hi Jacob the layout looks much better now following the DS recommendation. C7 and C6 are well connected to the IC.