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UCD9248: The function of some pins

Part Number: UCD9248
Other Parts Discussed in Thread: PTD08A010W

Recently, I download the schematic diagram of vc707 evaluation kit on Xilinx official website because of starting to use virtex-7 FPGA. Its power supply uses ucd9248 and ptd08a010w. I want to know the functions of some pins in ucd9248, such as DPWM and SRE pin. How do they control ptd08a010w? My understanding is that the DPWM signal controls the output voltage amplitude of the digital powertrain module, and SRE signal controls its output delay. I don't know whether it is correct or not. What are the functions of SEQ-1, SEQ-2, SEQ-3 and ENA pins? Finally, I want to know how to control the DPWM and SRE output signals of ucd9248. Thank you.

  • Hi Peter,
    Here's a quick breakdown of the pin functions...

    DPWM: signal generated by UCD9248. This signal consists of pulses varying in width in order to ensure that the output voltage of ptd08a010w matches the desired output.

    SRE: Does not control delay. It is a logic signal that enables the Switching Rectifier in the ptd08a010w module. When set high the module will operate in continuous conduction mode (CCM), when set low the module runs in discontinuous conduction mode (DCM). DCM is most efficient at lighter loads. This signal allows UCD9248 to switch in between these two modes to get maximum efficiency at a given load

    SEQ-1,SEQ-2,SEQ-3: logic signals that control power sequencing. They can be configured as inputs  or outputs.


    EAN/EAP: These are differential sense lines that UCD9248 uses in order to accurately measure the output voltage of the power stages it is controlling. This signal is used to dynamically vary the width of the DPWM pulses so that the output voltage matches the desired voltage.

    You change the settings of UCD9248 by programming it with the Fusion Power Designer:

  • vc707_Schematic_xtp135_rev1_0.pdfThank you for your reply.But I do not know the specific function of SEQ.For example,there are three ucd9248 in schematic of vc707 evaluation kit.I found that the SEQ-1 and SEQ-2 of all chips are connected together while the SEQ-3 of first chip is conected to a equivalent circuit as below.The SEQ-3 of other two chips are unconnected.Can you tell me what does it mean?

  • I did some digging in the VC707 user guide (found here)
    That UCD9248 you've shown (U42) is controlling three modules, while the others are only controlling two. The additional module is probably being enabled by a SEQ signal from the FPGA itself (pg.4 of the schematic you attached, it's level shifted on pg.39). One can use the program I mentioned earlier to tell UCD9248 how to use the SEQ pins. I suspect that that SEQ3 pin is used as an enable controlled by the FPGA. 

  • Thanks for your help.I think I should read user guide to find the meaning of SEQ pin.