UCC27538: OUTH protection

Hi Tune,

Thanks for reaching to the High Power Drivers team, my name is Mamadou Diallo and I will help address your questions.

The output stage of this device does not have zenner diode, the image below shows the output configuration of the driver.

The body diodes of the internal MOSFETs at the stage help protect the driver from switching overshoot/undershoot.

What are you hoping to accomplish with diode D50 on the OUTL pin?

Also R51 and C37 are really not necessary. Are you trying to implement a filter at the gate?

When input goes low, the driver's OUTH pin is in high impedance mode since the OUTH and OUTL are not tied together.

Also you may want to consider increasing C38 to >=1uF as recommended in the datasheet to properly bias the driver and place it very close to the VDD pin for effective noise filter. 

Thanks in advance for elaborating and I look forward to hearing from you.

Regards,

-Mamadou

Hi Mamadou

Thank you for the quick answer:-)

I use it to drive a P-channel MOSFET, and D50 is used to ensure that the MOSFET is not turned on durring startup.

R51 and C37 is used to drive the gate without exceeding the VGS rating.(It cannot take 21V) Notice the MOSFET is turned on when UCC27538 input is low.

C38: I have more than the 100nF on the VDD PIN, just placed elsewhere on the schematic.

"When input goes low, the driver's OUTH pin is in high impedance mode since the OUTH and OUTL are not tied together."

I do not think this is the case, and the reason for my question. I have looked at the datasheet and seen the principal schematic of the output stage. The problem is that OUTH is pulling down to 8V if I leave OUTL not connected.

Can you ask the design team for more information about this output?

Regards,

Tune

Hi Tune,

Thanks for your patience and previous explanation of your circuit.

I've reached out to my design and I should hear from them by the end of the week.

In the meantime, (out of curiosity, if possible) can you share application and/or end equipment for this design?

Also, you specified that VP=21V, VN=0V, What is VZ?

Regarding the following subject, "When input goes low, the driver's OUTH pin is in high impedance mode since the OUTH and OUTL are not tied together."

I will refer you to Table 5 (I/O logic truth table) of the datasheet where we specify the driver's output pins behavior:

Thanks again for your time and patience.

Regards,

-Mamadou

Hi Mamadou

Thank you, looking forward to their response.

VZ is about 6V, but not important for my question.

It is for a gatedriver driving large IGBT's.

Regards,

Tune

I have added some measurement below i just made to understand the output better. I build a small test board, and tried to keep it as simple as possible with a pull up resistor, and also tried with much more capacitive loading than what I have in the real circuit.

I hope you can provide a more detailed diagram, than what is provided in the datasheet, and tell me if it is safe to use the device this way.

Looking forward to your response!

Regards,

Tune

Hi Don

"Please verify the logic table in the d/s. I don't think you want to tie INH and INL together."

According to the datasheet they are called IN1 and IN2 and should follow the truth table given in the datasheet. I Do not understand why I cannot tie them together.

According to this table OUTH should be high when IN1 and IN2 is high. This is also what i see when i test the device:

When IN1 and IN2 is Low, OUTH should be high impedance according to the table. This I do not see when I test the device. Please explain to me why OUTH is ~8V when IN1 and IN2 is low. Se below test:

Regards,

Tune

Ok, Mateo

Looking forward to your response:-)

Tune

Hello Tune, 

Unfortunately, I did not receive samples before the holiday break.

I will give up an update by the end of Monday 11/26. Thank you for your patience. 

Regards,
Mateo

Hi Tune,

I was able to replicate your waveforms on the bench shown below with our control units.

There seems to be clamping at 8.2V when VDD=15V. 

The clamping seems to go up to 10.5V at higher VDD(30V). I am still working with design to get to the bottom of it.

I will update as soon as I get a breakthrough. 

Thanks.

Regards,

-Mamadou

Hi Mamadou

I cannot see your pictures, could you add them again?

I also see the 10.5V clamping at 30V.

Looking forward to more feedback:-)

Regards,

Tune

Hi Tune,

Sorry about the missing images.

My plots do confirm your observations with clamping at 8V.

I suspected the 2.2kOhms pullup resistor to be creating some sort of resistor divider with the internal pullup resistor which may have been the reason for the 8.2V so I removed the 2.2kohms and below were some plots at different frequencies:

The plots still shows clamping however smaller magnitude at 5V and there seems to be a frequency dependency with 1kHz driver eventually pulling all the way down to 0V. 

Yes, lets hope the design team can explain what we see...

Thanks!

Tune

Hi Mamadou

Thank you for the feedback!

Can you try to make a drawing on how this Zener diode is connected. If it is connected from OUTH to GND, it will be conducting large current when OUTH is high. Is it connected between OUTH and OUTL?

It is important for my circuit that D50 has higher voltage than UCC27538's UVLO threshold, to prevent Q1 to turn on at lower voltage durring startup.(see schematic in my first post)

Durring our testing, the device did not seem to be damaged.(Maybe it is stressed without knowing it) Can you give a rating for the internal Zener diode?

(In out test circuit we had a 2.2kohm and a 47nF capacitor connected to the output,  without visible damage to the IC. In my circuit it is about 10kohm and ~1nF, which should stress the IC even less. It would be nice to know if this long term, will stress the IC.)

Regards,

Tune

Hi Mamadou

You have been very helpful! I still have a few questions, that I hope you will help me with, so I do not discard my good design for no reason:-)

Here is the schematic:

Questions:

Ragards,

Tune