Hi ,
I am using UC3854B PWM IC in my PFC design. I am referring functional block diagram and found SR flip flop inputs named as RRS. Is it a printing mistake or else some thing else.
I feel one is clock (CLK) and other two are S & R inputs. Can any one clarify this.
Thanks
Seshaiah
Hello Seshaiah,
I think you are referring to this block diagram:
The diagram shows a flip flop with two reset (R) inputs.
The gate drive is reset (low) by the PKLMT condition and also when the current amplifier output exceeds the CT (ramp)
The gate drive is set high every clock cycle by the system oscillator (OSC)
Regards
John
