Other Parts Discussed in Thread: CSD17551Q3A,
Hello.
I would appreciate some directions on how to use the formulae in the data sheet, section 10.2, especially section 10.2.2.5 (Power MOSFETs).
My design has the following requirements (simplified for worst case analysis):
Vin: 12V +/- 10%
Vout: 10 to 15V (worst case, considering minimum and maximum voltage of a ten-cell NiMH pack)
Pout: 60W total, including current to charge the pack. So, Imax = 6A (Vout=10V) and Imax = 4A (Vout = 15V).
About transistors, I had several questions while throwing the formulae in a spreadsheet (I used the same FETs as the EVM (CSD17551Q3A).
1- What values for Qgd, Qgs, Qg? I used values from FET data sheet for Qgd and Qgs and Qg @ 6V (VREGN)
2- What Vplt? I used 2.5V based on figure 4 of the FET data sheet and some application notes.
3- What Ron and Roff? BQ25713’s data sheet has several values depending on driver output so I took the largest values I found for turn on and turn off resistances, respectively 7.6 and 4.6R and added to 3R (series gate resistance of the FET).
4- For dynamic power loss, I used the highest Fswitch, 920kHz (for 2.2uH inductor)
With these values, I found:
1- ton and toff ~8ns.
2- Ptop ~1.4W for Vin=12.2V, Vout=15V, Iout=6A (see requirements below).
3- P bottom ~0.09W, worst case (Iout=4A,
I first thought ton and toff were underestimated but Ptop makes some sense to me. However, I would like to have a feedback about the assumptions above.
About capacitors, I would like to know how critical are the values indicated for Cin and Cout in the data sheet and the EVM, i.e. 4*10uF + 10uF (Cin) and 6*10uF. The reason I am asking this is I am going to use ceramic capacitors, namely 10uF x 25V, 1206. Six capacitors derated must get to around 40uF. I would like to know if it is OK. Also, is it OK using ceramics only from stability point of view?
One last note, about the data sheet: Fig. 46 show the capacitors as mF instead of uF.