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BQ25713: Key components (transistors/capacitors/inductor) dimensioning.

Part Number: BQ25713
Other Parts Discussed in Thread: CSD17551Q3A,

Hello.

 

I would appreciate some directions on how to use the formulae in the data sheet, section 10.2, especially section 10.2.2.5 (Power MOSFETs).

 

My design has the following requirements (simplified for worst case analysis):

Vin: 12V +/- 10%

Vout: 10 to 15V (worst case, considering minimum and maximum voltage of a ten-cell NiMH pack)

Pout: 60W total, including current to charge the pack. So, Imax = 6A (Vout=10V) and Imax = 4A (Vout = 15V).

 

About transistors, I had several questions while throwing the formulae in a spreadsheet (I used the same FETs as the EVM (CSD17551Q3A).

1-     What values for Qgd, Qgs, Qg? I used values from FET data sheet for Qgd and Qgs and Qg @ 6V (VREGN)

2-     What Vplt? I used 2.5V based on figure 4 of the FET data sheet and some application notes.

3-     What Ron and Roff? BQ25713’s data sheet has several values depending on driver output so I took the largest values I found for turn on and turn off resistances, respectively 7.6 and 4.6R and added to 3R (series gate resistance of the FET).

4-     For dynamic power loss, I used the highest Fswitch, 920kHz (for 2.2uH inductor)

With these values, I found:

1-     ton and toff ~8ns.

2-     Ptop ~1.4W for Vin=12.2V, Vout=15V, Iout=6A (see requirements below).

3-     P bottom ~0.09W, worst case (Iout=4A,

I first thought ton and toff were underestimated but Ptop makes some sense to me. However, I would like to have a feedback about the assumptions above.

 

About capacitors, I would like to know how critical are the values indicated for Cin and Cout in the data sheet and the EVM, i.e. 4*10uF + 10uF (Cin) and 6*10uF. The reason I am asking this is I am going to use ceramic capacitors, namely 10uF x 25V, 1206. Six capacitors derated must get to around 40uF. I would like to know if it is OK. Also, is it OK using ceramics only from stability point of view?

 

One last note, about the data sheet: Fig. 46 show the capacitors as mF instead of uF.

  • Hey Elder,

    Are you looking for feedback on whether you did the calculations correctly or selected the right values from the MOSFET datasheet?

    As far as the output capacitors, we recommend a minimum of 60-uF on the output and this to account for DC derating of ceramics. And ceramics are better for this device than other capacitor from a stability perspective. The input capacitors should have enough to filter high frequency content that comes from the HSFET switching event. We typically put a minimum of 40- to 60-uF as well.


    Regards,
    Joel H
  • >>Are you looking for feedback on whether you did the calculations correctly or selected the right values from the MOSFET datasheet?

    The latter. The formulae are OK. I just am not sure I used the correct parameters (Qgd, Qgs, Qg etc.) to do the math, particularly those that must be derived or inferred.

    So, are my inferences on 1 to 4 above OK? In other words, what parameters would you use for 1 to 4 above? Once I know I used parameters that are OK, then I understood the concept and my results will make sense.

    Re. capacitors, I will add some to compensate for the DC derating.

    Thank you very much for your support.

    BR

    Elder.

  • Hey Elder,

    1. From your equations in the datasheet Design section, you do not need the value of Qg unless you are doing a comparison between FETs in terms of selection. But for the remaining equations, all that is needed is Qgd, Qgs, and Rdson of the FETs to estimate the power loss through the power stage.

    2. Plateau voltage looks about right from the MOSFET datasheet.

    3. Your assumption is correct to take the Roff and Ron values of the drivers PLUS the FET series gate resistance (RG). One thing I want to point out however it which Gate Drivers are active for your calculation. Based on your input and output requirements, you will sometimes be in boost mode, and other times in buck mode. So select the values appropriately for the mode of operation. I am not sure if you included this in your calculation, or which mode of operation you were calculating around.

    4. That is fine.

    As far as all the number, you will also want to go back and double check your calculations depending on the operating mode you've selection. Another important parameter is the duty cycle (D). Remember that this value will also be affected by the operating mode. In buck mode, D is Vout/Vin, but not in boost mode. Also note that ton in boost mode pertains to the LSFET and not the HSFET.


    Regards,
    Joel H
  • Hello, Joel.

    Thank you for your clarification. It is good to know I am on the right path.

    About Qg, good point. I was wondering what those FOM figures were for. :)

    About your answer to 4, you mean Ptop refers to the Q3 when in boost mode? It makes sense to me as it is the heavy weight lifter in boost mode but naming (top/bottom side) may be misleading.

    BR

    Elder.

  • Hello, Joel,

    Another question that just ocurred to me: ICHG in the formulae is the total DC (average) current passing through the inductor, right? I mean, current used by the load connected to VSYS plus current charging the battery pack.

    Thanks.

    Elder.

  • Hey Elder,

    To your first reply: The equations in and nomenclature in the datasheet are really referring to buck mode. You would have to change certain parameters, including which FET becomes the synchronous and which FET becomes the active one, as well as adjust the Duty cycle calculations.

    To your second reply: ICHG as you stated, should really be the average RMS current processed by the inductor, whether in boost or buck mode. In buck mode, it will be the sum of the SYS and BAT current. In boost mode, it will be a function of the efficiency and power conversion based on those same loads.


    Regards,
    Joel H
  • Hi, Joel.

    I was aware of the duty cycle change according to the mode and I used both to do the math.

    I will review the math anyway but at least I know I am on the right path (mostly).

    Thank you very much for your great support.

    BR.

    Elder.