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TPS54394: via distances in layout guideline

Part Number: TPS54394


Figure 27 of the TPS54394 datasheet, there are these recommendations:
a.       Keep vias > 3-4 mm from input capacitors
b.      Keep vias > 3-4 mm from output capacitors
c.       Keep output vias > 25 mm from input vias

What is the purpose of keeping these via distances?

Thank you!



  • Hi Alberto,

    For the 3-4mm instruction, it helps to avoid noise scattering, especially GND plane. Input loop is high di/dt path and it's very noisy. Vias are nothing but small inductors and capacitors. So, keeping them some distance from noise source is good.
    Similarly, keeping output vias from the noisy input vias is also important.

  • Hi Hao,

    thanks for your response.

    I just want to confirm: if the vias are used as ground return for other components those would preferably be placed at some distance to avoid the HF swtiching current of the power loop to flow through them. Similarly if they are a different net (especially if high impedance/ high BW), the distance would prevent noise coupling.

    But if the vias are intended to the the ground return for the power loop, those should be as close as possible to the capacitors as to reduce board inductance, agree?

    Thank you much!

    Best regards,


  • Hi,

    Actually, most of the return current of power would run on the copper on top layer, rather than go through the vias.