LP38853: Reverse current

Hi PAN-M,

Yes, a reverse current will flow under the following conditions:

• The output voltage exceeds the input voltage
• The output voltage is not being held at the regulation output by a downstream component
• EN is high
• UVLO exceeds the threshold

This is because EN and BIAS enable and power the internal control loop, allowing it to respond to changes in the output voltage. If the input voltage drops below the output, and the output is not held up, the output voltage will also drop as the output capacitor discharges. The control loop attempts to continue regulating by driving the gate of the pass FET to the BIAS voltage. However, since the input voltage is lower than the output voltage, driving the gate forces the pass FET to conduct in the reverse (OUT to IN) direction until the output capacitor is fully discharged. This behavior is explained in the last paragraph of the Reverse Voltage Feature Description in the datasheet:

The power n-channel MOSFETs are not back to back coupled as one of the main advantages of using n-channel pass FETs is the ability to achieve very low dropout voltages. Adding another FET in series for back to back coupling would increase the dropout voltage. Although the pass FETs for this device have the same gate drive, they are not in series; the sources of the MOSFETs are tied together. This can be seen in the functional block diagram:

Thanks,

Gerard