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TPS7A49: Sense wire / connection

richard wiskin
Prodigy 50 points
Part Number: TPS7A49
Other Parts Discussed in Thread: TPS7A30-49EVM-567,

Could you confirm the correct configuration with the sense line. It appears that the sense line should make contact with the regulated output at the point where the circuit being powered (power entry point) is located. Can you confirm this please.
Also where would the best location be for the capacitor referred to as CFF 10nF.

I ask this because your evaluation board ties the sense line to the output voltage, on the actual board, rather than offering a V out / GND out and Sense out. Presumably this is just for convenience and is not the best way to configure the device.

  • 0
    TI__Guru 55940 points

    Hi Richard,

    Correct TPS7A30-49EVM-567 does not offer sense test points the way that our newer EVMs do.  This particular EVM has a silkscreen box around the complete LDO solution in order to better show the solution size to customers.  Generally LDOs are placed local to their loads and would have a similar solution size to the silkscreen box rather than the full EVM.

    The advantage of a sense testpoint local to the LDO output is that your measurement will not include the voltage drop due to the resistance in the Vout plane.  In an application you could account for some of this voltage drop by placing the feedback network closer to your load; however, it is important that the feedback network connection comes before any ferrite bead or inductor.

    As on the EVM, we generally recommend that the feedforward capacitor be placed next to the top resistor in the feedback networks resistor divider.

    Very Respectfully,

    Ryan

  • 0 in reply to Ryan Eslinger
    Prodigy 50 points

    Hi Ryan, thanks for the reply. This seems to be the optimal layout and includes a separate path for the sense line, but no CFF shown. Sounds like you want it placed In parallel with R1?

    I noticed yesterday how sensitive the circuit is to the length and path that the sense line takes away from the board. I am inclined to send it down a short, shielded cable along with Vout and Gnd.

  • 0 in reply to richard wiskin
    TI__Guru 55940 points

    Hi Richard,

    Thank you for the reply.  I apologize for misunderstanding which layout example to which you were referring.  In Figure 37 the "sense line"  is routed to R1 under the Cout and is intended to be connected to Vout close to the load but before any large amount of inductance.  The purpose of connecting the R1 to Vout closer to the load is that you can reduce the voltage drop due to the resistance of the Vout plane; however, for stability it is important to minimize any inductance within the LDO control loop.

    The resistor divider and "sense line" are the main parts of the LDOs feedback loop.  The internal Error Amp drives the pass device so that Vout divided by the resistors is equal to the internal reference.  Any noise picked up in the feedback loop can impact the output voltage. 

    Yes a Cff would be placed in parallel with R1.

    Very Respectfully,

    Ryan

  • 0 in reply to Ryan Eslinger
    Prodigy 50 points
    Hi Ryan
    You didn't misunderstand me, so no need to apologise. The EVM is something I ordered to evaluate the device, the second layout seems more advanced. I am now looking at doing my own PCB layout. The only question all this raises is that if the only benefit of the sense line being connected directly to the load is to reduce voltage drop, then perhaps if stability and noise are my key criteria, I should just connect the V sense to the output nearest to the device.

    The actual voltage variation is a secondary consideration (steady state).
    I perhaps misunderstood the benefit of having V sense connected to the load directly, thinking it enables compensation for noise picked up at the load. Seems the best solution is to collocate the reg and the load anyway.

    best wishes Richard
  • 0 in reply to richard wiskin
    TI__Guru 55940 points

    Hi Richard,

    My recommendation for laying out TPS7A49 (or really any LDO) would be more similar to the EVM.  Below I have circled in red the ideal location of the load.  In this way you will benefit from having the feedback network close to the load as well as minimize any parasitic that would adversely impact the LDO performance.  The load will likely have its own passive components as well, but the main idea is to place the LDO as close to the load as possible for best performance.

    Very Respectfully,

    Ryan