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Original question:

Advice regarding TPS61032 Can some one verify my setup

TPS61032: Verify layout of TPS61032 RSA QFN package

Dave Young
Intellectual 520 points
Part Number: TPS61032

Hello-

I'm laying out the TPS61032RSA which has the QFN package and would like to see if someone can help me by reviewing my layout. I looked at the EVM and datasheet, but could only find example layouts for the TSSOP packages.

I am having to make some design compromises in order to make it all work. Since the switch node pin is in between the PGND and VOUT pins, I have to chose between maintaining an uninterrupted GND pour between the input and output caps, or keeping the SW node all on the same layer. I think I have a pretty good layout based on the layout guidelines in the datasheet, but wanted to get another set of eyes on it. I'm using a 4-layer board, with red being top, green being a ground plan at layer 2, blue being SYS_VBAT on layer 3, and blue being bottom layer which is the layer that connects the two switch node vias.

Here are the schematic and layout images.:

Thanks!

Dave

  • 0
    TI__Mastermind 21565 points
    Hi Dave:
    Sorry that I couldn't see your images. May be something wrong with my computer or explorer.
    Please see the application note first before I see the image properly: Five Steps to a Good PCB Layout of the Boost Converter: www.ti.com/.../slva773
  • 0 in reply to Minqiu Xie
    Intellectual 520 points

    Thanks for the reply. Sorry you couldn't see the images -- I can't either in the post (I pasted them directly in the editor, which apparently didn't work).

    I've attached them here. The layout shows a couple different views to display the SW node trace on the bottom layer (dark blue), and the relief of the power plane (light blue), and the ground pour on layer 2 (green).

    Dave

  • 0 in reply to Dave Young
    TI__Mastermind 21565 points
    Hi Dave:
    Great to see the your clear imagine. It's professional.
    I think the layout is OK. And it's better if you minimize the road from Vout to C39 to GND. And make C42 closer to IC. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
    Besides, there is an example layout in 13.2 in datasheet. www.ti.com/.../tps61032
  • 0 in reply to Minqiu Xie
    Intellectual 520 points

    Thanks! I appreciate the feedback. I'll look at implementing your changes. Although what does it mean to 'minimize the road from Vout to C39 to GND'? Do you mean make the trace thinner? Or try to move a component? I'm not sure how I would move the component to shorten the traces.

    The example layout on the datasheet was helpful, but doesn't show SMT pads, making it difficult to use. For instance their output capacitor 2 goes over a fat trace  which would force it to be in a very large package which would mean the inductor would have to be farther from the IC than I have it placed in my design. Also, they don't have any decoupling cap (C42 on my schematic).

  • 0 in reply to Dave Young
    TI__Mastermind 21565 points

    Hi Dave:
    Thanks for your kindly words. Besides, I thought the layout of Cout is higher priority than inductance. If there is no much space for layout, some Via could help the loop better.