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ISO5451-Q1: Paralleling of Power MOSFET'S to control the Output state of gate driver

Part Number: ISO5451-Q1

Hi Team,

In the functional block diagram of ISO5451-Q1, at page no.11, section 9.2

The diagram shows the paralleling of Power MOSFET's in complementary logic, where PMOS is in parallel with NMOS.

I would like to know why is the NMOS in parallel with PMOS.

Can you please provide with some information regarding the same.

Regards,

Komal Divate

  • Hi Komal,

    Thanks for your interest in our part, my name is Mamadou Diallo, I am an applications engineer in the high power drivers group.

    The parallel N-channel MOSFET is there to provide a brief boost in the peak-sourcing current of the driver, allowing to achieve faster turn-on transient. This N-channel FET is only active for a brief period when the output is changing states from low to high and remains off the rest of the time.
    This helps the driver deliver the effective necessary peak current in the miller plateau region of the power FET.

    Please let us know if you have further questions.

    Regards,

    -Mamadou