Hi Team,
In the functional block diagram of ISO5451-Q1, at page no.11, section 9.2
The diagram shows the paralleling of Power MOSFET's in complementary logic, where PMOS is in parallel with NMOS.
I would like to know why is the NMOS in parallel with PMOS.
Can you please provide with some information regarding the same.
Regards,
Komal Divate