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CSD19506KCS: peak diode recovery dV/dt

Sean Cashin
Genius 14156 points
Part Number: CSD19506KCS

What is the dV/dt rating of this switch? Do you have a recommendation for another switch specified for >2V/ns?

Best regards,

Sean

  • 0
    TI__Mastermind 29525 points
    Hi Sean,
    Thanks for the questions. We don't spec dV/dt in our datasheets. It is my understanding that there are two mechanisms to be concerned with: (1) C x dV/dt induced turn on thru the Miller capacitance and (2) activation of the parasitic bipolar transistor. The first is well understood and can be minimized by design of the FET and external driver circuit. In the FET, we target a QGD/QGS ratio < 1 and minimize the internal gate resistance, RG. Externally, the gate drive circuit needs to have a very strong pull down as this equivalent resistance is in series with the internal RG. For the CSD18506KCS, the charge ratio is 20nC/37nC = 0.54 < 1, and RG = 1.3ohm (typ) & 2.6ohm (max). The parasitic bipolar effect is minimized by design of the FET.

    I'm checking with a colleague who tested our MV FETs and will update you as soon as I have more information.
  • 0 in reply to John Wallace1
    TI__Mastermind 29525 points
    Hi Sean,
    I did some more research and followed up with my colleague. We don't need to worry about the parasitic bipolar turning on. That is taken care of in the design of the FET and verified with elevated temperature UIS testing. CdV/dt turn-on is very much related to the external drive circuit. Using a simplified FET model, we can calculated dV/dt <= VTH/(RGxCGD), where VTH = threshold voltage, RG = total gate resistance (internal + external driver) and CGD = gate-to-drain capacitance (specified as CRSS in the datasheet). It's not exact because CGD varies with VDS but it will give you a good idea how fast you can switch. Using the datasheet values (min VT & max CRSS) and assuming a total RG = 5ohms: dV/dt <= 2.1V/(5ohms x 55pF) = 7.6V/ns. I would probably derate this somewhat. Even with 50%, you're still OK with 2V/ns. As always, you need to minimize the loop area of the gate-source (driver) and drain-source loops as parasitic inductance can impact the ability to hold the gate low when the FET is off and it's drain voltage swings up rapidly.