TPS7B6350EVM: TPS7B6350QPWPRQ1 about RθJA

Hi,

For the given operating conditions, the power dissipated in the pass transistor is calculated as:

Pd = (Vin - Vout) * Iout = (12.7 V - 5.0 V) * 0.06 A = 0.462 W

RθJA,max can then be calculated for a given ambient temperature:

RθJA,max = (Tj,max - Ta) / Pd = (150 C - Ta) / 0.462 W

The PCB must be designed to ensure that RθJA is less than RθJA,max calculated above. This will prevent the junction temperature exceeding the absolute maximum rating of 150 C. 

1. The RθJA value specified in the datasheet is derived with a model of the industry standard JEDEC High-K Thermal Test Board described in JESD51-7. This is a 4-layer, 9 square inch PCB (3 in by 3 in). You can register for free here: https://www.jedec.org/user/register. After registering, you can access JESD51-7 here: https://www.jedec.org/system/files/docs/jesd51-7.PDF.
2. RθJA is inversely proportional to the number of thermal vias. The following application reports discuss this topic:

• • PowerPAD Thermally Enhanced Package, Section 2.4 Thermal Vias: http://www.ti.com/lit/an/slma002h/slma002h.pdf
  • A Guide to Board Layout for Best Thermal Resistance for Exposed Packages: http://www.ti.com/lit/an/snva183b/snva183b.pdf

Please see the following application reports for additional information regarding RθJA and other thermal metrics:

Semiconductor and IC Package Thermal Metrics: http://www.ti.com/lit/an/spra953c/spra953c.pdf

Using New Thermal Metrics: http://www.ti.com/lit/an/sbva025/sbva025.pdf

These and other application reports discussing thermal metrics and performance can be found in the Packing resources section of the TI website:

http://www.ti.com/support-packaging/packaging-resources/SMT-and-application-notes.html

Thanks,

Gerard